diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index ecf8ef8..beb2244 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -101,6 +101,15 @@
 	out[1] = ret.hi;
 }
 
+/*
+ * Ironlake memory I/O timings are located in scan chains, accessible
+ * through MCHBAR register groups. Each channel has a scan chain, and
+ * there's a global scan chain too. Each chain is broken into smaller
+ * sections of N bits, where N <= 32. Each section allows reading and
+ * writing a certain parameter. Each section contains N - 2 data bits
+ * and two additional bits: a Mask bit, and a Halt bit.
+ */
+
 /* OK */
 static void write_1d0(u32 val, u16 addr, int bits, int flag)
 {