chip soc/intel/meteorlake

	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C2
	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C1
	register "usb2_ports[3]" = "USB2_PORT_MID(OC3)"		# Type-A Port A0
	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C3
	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"		# Type-A Port A4
	register "usb2_ports[6]" = "USB2_PORT_MID(OC3)"		# Type-A Port A1
	register "usb2_ports[7]" = "USB2_PORT_MID(OC3)"		# Type-A Port A2
	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"		# Type-A Port A3
	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth

	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type-A Port A0
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type-A Port A1

	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)"
	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)"
	register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)"

	# Enable Display Port Configuration
	register "ddi_ports_config" = "{
		[DDI_PORT_1] = DDI_ENABLE_HPD,
		[DDI_PORT_2] = DDI_ENABLE_HPD,
		[DDI_PORT_3] = DDI_ENABLE_HPD,
		[DDI_PORT_4] = DDI_ENABLE_HPD,
	}"

	register "serial_io_i2c_mode" = "{
		[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
		[PchSerialIoIndexI2C4] = PchSerialIoPci,
		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
	}"

	# Intel Common SoC Config
	#+-------------------+---------------------------+
	#| Field             |  Value                    |
	#+-------------------+---------------------------+
	#| I2C4              | cr50 TPM. Early init is   |
	#|                   | required to set up a BAR  |
	#|                   | for TPM communication     |
	#+-------------------+---------------------------+
	register "common_soc_config" = "{
		.i2c[4] = {
			.early_init = 1,
			.speed = I2C_SPEED_FAST,
			.rise_time_ns = 600,
			.fall_time_ns = 400,
			.data_hold_time_ns = 50,
		},
	}"

	device domain 0 on
		device ref pcie_rp7 on
			# Enable LAN1 Card PCIE 7 using clk 2
			register "pcie_rp[PCH_RP(7)]" = "{
				.clk_src = 2,
				.clk_req = 2,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
			chip drivers/net
				register "customized_leds" = "0x05af"
				register "wake" = "GPE0_DW0_01" # GPP_D01
				register "device_index" = "0"
				register "add_acpi_dma_property" = "true"
				device pci 00.0 on end
			end
		end	# PCIE7 LAN1 card
		device ref pcie_rp10 on
			# Enable LAN0 Card PCIE 10 using clk 8
			register "pcie_rp[PCH_RP(10)]" = "{
				.clk_src = 8,
				.clk_req = 8,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
			chip drivers/net
				register "customized_leds" = "0x05af"
				register "wake" = "GPE0_DW1_04" # GPP_E04
				register "device_index" = "1"
				register "add_acpi_dma_property" = "true"
				device pci 00.0 on end
			end
		end	# PCIE10 LAN0 card
		device ref pcie_rp11 on
			# Enable SSD Card PCIE 11 using clk 7
			register "pcie_rp[PCH_RP(11)]" = "{
				.clk_src = 7,
				.clk_req = 7,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end	# PCIE11 SSD card
		device ref i2c4 on
			chip drivers/i2c/tpm
				register "hid" = ""GOOG0005""
				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E03_IRQ)"
				device i2c 50 on end
			end
		end
	end

end