mb/google/rex/var/deku: Enable LAN0, LAN1
google/deku is a Chromebox featuring two LAN ports.
Add overridetree.cb entry to configure the LAN0 LAN1 devices.
BUG=b:305793886
TEST=Built FW image correctly.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79292
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/mainboard/google/rex/variants/deku/gpio.c b/src/mainboard/google/rex/variants/deku/gpio.c
index 324c236..94c06e8 100644
--- a/src/mainboard/google/rex/variants/deku/gpio.c
+++ b/src/mainboard/google/rex/variants/deku/gpio.c
@@ -144,7 +144,7 @@
/* GPP_D00 : net NC is not present in the given design */
PAD_NC(GPP_D00, NONE),
/* GPP_D01 : [] ==> LAN1_PCIE_WAKE_ODL */
- PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PLTRST, LEVEL, INVERT),
+ PAD_CFG_GPI_SCI_LOW(GPP_D01, NONE, DEEP, EDGE_SINGLE),
/* GPP_D02 : [] ==> LAN1_PERST_L */
PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG),
/* GPP_D03 : net NC is not present in the given design */
@@ -199,7 +199,7 @@
/* GPP_E03 : [] ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_E04 : [] ==> LAN0_PCIE_WAKE_ODL */
- PAD_CFG_GPI_IRQ_WAKE(GPP_E04, NONE, PLTRST, LEVEL, INVERT),
+ PAD_CFG_GPI_SCI_LOW(GPP_E04, NONE, DEEP, EDGE_SINGLE),
/* GPP_E05 : [] ==> WLAN_PCIE_WAKE_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_E05, NONE, PLTRST, LEVEL, INVERT),
/* GPP_E06 : GPP_E06_STRAP ==> Component NC */
diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb
index 4dca7e2..35ce9b46 100644
--- a/src/mainboard/google/rex/variants/deku/overridetree.cb
+++ b/src/mainboard/google/rex/variants/deku/overridetree.cb
@@ -55,6 +55,36 @@
}"
device domain 0 on
+ device ref pcie_rp7 on
+ # Enable LAN1 Card PCIE 7 using clk 2
+ register "pcie_rp[PCH_RP(7)]" = "{
+ .clk_src = 2,
+ .clk_req = 2,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip drivers/net
+ register "customized_leds" = "0x05af"
+ register "wake" = "GPE0_DW0_01" # GPP_D01
+ register "device_index" = "0"
+ register "add_acpi_dma_property" = "true"
+ device pci 00.0 on end
+ end
+ end # PCIE7 LAN1 card
+ device ref pcie_rp10 on
+ # Enable LAN0 Card PCIE 10 using clk 8
+ register "pcie_rp[PCH_RP(10)]" = "{
+ .clk_src = 8,
+ .clk_req = 8,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip drivers/net
+ register "customized_leds" = "0x05af"
+ register "wake" = "GPE0_DW1_04" # GPP_E04
+ register "device_index" = "1"
+ register "add_acpi_dma_property" = "true"
+ device pci 00.0 on end
+ end
+ end # PCIE10 LAN0 card
device ref pcie_rp11 on
# Enable SSD Card PCIE 11 using clk 7
register "pcie_rp[PCH_RP(11)]" = "{