mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version
cr50 firmware revisions starting at 0.5.5 and later are able to extend
their IRQ pulses to be a minimum of 100us long. This change will enable
cr50 long interrupt pulses when it detects the feature is supported by
the detected firmware version. If the capability was detected, then
GPIO PM will be enabled for the device, otherwise it will be disabled.
BUG=b:202246591
TEST=boot brya0, check console logs for the correct message, and
verify the GPIO PM registers.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61722
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c
index 488eb88..42536bb 100644
--- a/src/mainboard/google/brya/mainboard.c
+++ b/src/mainboard/google/brya/mainboard.c
@@ -1,12 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpigen.h>
#include <baseboard/variants.h>
#include <device/device.h>
+#include <drivers/tpm/cr50.h>
+#include <drivers/wwan/fm/chip.h>
#include <ec/ec.h>
#include <soc/ramstage.h>
#include <fw_config.h>
-#include <acpi/acpigen.h>
-#include <drivers/wwan/fm/chip.h>
+#include <security/tpm/tss.h>
+#include <soc/gpio.h>
+#include <soc/ramstage.h>
WEAK_DEV_PTR(rp6_wwan);
@@ -28,6 +32,29 @@
void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{
+ int ret;
+
+ ret = tlcl_lib_init();
+ if (ret != VB2_SUCCESS) {
+ printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret);
+ return;
+ }
+
+ if (cr50_is_long_interrupt_pulse_enabled()) {
+ printk(BIOS_INFO, "Enabling GPIO PM b/c CR50 has long IRQ pulse support\n");
+ config->gpio_override_pm = 0;
+ } else {
+ printk(BIOS_INFO, "Disabling GPIO PM b/c CR50 does not have long IRQ pulse "
+ "support\n");
+ config->gpio_override_pm = 1;
+ config->gpio_pm[COMM_0] = 0;
+ config->gpio_pm[COMM_1] = 0;
+ config->gpio_pm[COMM_2] = 0;
+ config->gpio_pm[COMM_3] = 0;
+ config->gpio_pm[COMM_4] = 0;
+ config->gpio_pm[COMM_5] = 0;
+ }
+
variant_update_soc_chip_config(config);
}