soc/intel/skylake: Make use of common thermal code for SKL
This patch ensures skylake soc is using common thermal code
from intel common block.
TEST=Build and boot soraka
Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index bf1897c..75fcf9c 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -67,7 +67,6 @@
register "tdp_pl2_override" = "18"
register "psys_pmax" = "45"
register "tcc_offset" = "10"
- register "pch_trip_temp" = "75"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
@@ -201,6 +200,7 @@
#| I2C3 | Camera |
#| I2C4 | Audio |
#| I2C5 | Rear Camera & SAR |
+ #| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
@@ -241,6 +241,7 @@
.speed_mhz = 1,
.early_init = 1,
},
+ .pch_thermal_trip = 75,
}"
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"