diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 96a142a..ee1a543 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -171,19 +171,15 @@
 	unsigned long tmp;
 
 	/* IGD has to be enabled, GFXVTBAR set and enabled. */
-	if (is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten) {
+	const bool emit_igd = is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten;
+
+	/* First, add DRHD entries */
+	if (emit_igd) {
 		tmp = current;
 
 		current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
 		current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
 		acpi_dmar_drhd_fixup(tmp, current);
-
-		/* Add RMRR entry */
-		tmp = current;
-		current += acpi_create_dmar_rmrr(current, 0,
-				sa_get_gsm_base(), sa_get_tolud_base() - 1);
-		current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
-		acpi_dmar_rmrr_fixup(tmp, current);
 	}
 
 	/* DEFVTBAR has to be set and enabled. */
@@ -210,6 +206,15 @@
 		acpi_dmar_drhd_fixup(tmp, current);
 	}
 
+	/* Then, add RMRR entries after all DRHD entries */
+	if (emit_igd) {
+		tmp = current;
+		current += acpi_create_dmar_rmrr(current, 0,
+				sa_get_gsm_base(), sa_get_tolud_base() - 1);
+		current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
+		acpi_dmar_rmrr_fixup(tmp, current);
+	}
+
 	return current;
 }