soc/amd/stoneyridge: use common pm_set_power_failure_state functionality
The functionality to restore the previous power state after power was
lost that could previously be enabled by selecting
MAINBOARD_POWER_RESTORE in the mainboard's Kconfig can now be achieved
by selecting POWER_STATE_PREVIOUS_AFTER_FAILURE in the mainboard's
Kconfig instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I49c4a44ca2c4fa937a823c4eddf1618739c15114
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index adce99c..ccffe76 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -36,6 +36,7 @@
select SOC_AMD_COMMON_BLOCK_LPC
select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PI
+ select SOC_AMD_COMMON_BLOCK_PM
select SOC_AMD_COMMON_BLOCK_PSP_GEN1
select SOC_AMD_COMMON_BLOCK_S3
select SOC_AMD_COMMON_BLOCK_SATA
@@ -379,12 +380,4 @@
functionality isn't disabled, configuring it as an output and driving
it as 0 will cause a reset.
-config MAINBOARD_POWER_RESTORE
- def_bool n
- help
- This option determines what state to go to once power is restored
- after having been lost in S0. Select this option to automatically
- return to S0. Otherwise the system will remain in S5 once power
- is restored.
-
endif # SOC_AMD_STONEYRIDGE
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 74f2937..80a6c6b 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -34,10 +34,6 @@
#define PM_SERIRQ_MODE BIT(6)
#define PM_SERIRQ_ENABLE BIT(7)
-#define PM_RTC_SHADOW 0x5b /* state when power resumes */
-#define PM_S5_AT_POWER_RECOVERY 0x04 /* S5 */
-#define PM_RESTORE_S0_IF_PREV_S0 0x07 /* S0 if previously at S0 */
-
#define PM_EVT_BLK 0x60
#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */
#define PCIEXPWAK_STS BIT(14)
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 28310ce..b7d7b5e 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -17,6 +17,7 @@
#include <amdblocks/acpimmio.h>
#include <amdblocks/lpc.h>
#include <amdblocks/acpi.h>
+#include <amdblocks/pmlib.h>
#include <amdblocks/smbus.h>
#include <amdblocks/smi.h>
#include <soc/southbridge.h>
@@ -353,6 +354,7 @@
/* After console init */
void bootblock_fch_init(void)
{
+ pm_set_power_failure_state();
fch_print_pmxc0_status();
}
@@ -453,12 +455,6 @@
void fch_final(void *chip_info)
{
- uint8_t restored_power = PM_S5_AT_POWER_RECOVERY;
-
- if (CONFIG(MAINBOARD_POWER_RESTORE))
- restored_power = PM_RESTORE_S0_IF_PREV_S0;
- pm_write8(PM_RTC_SHADOW, restored_power);
-
struct global_nvs *gnvs = acpi_get_gnvs();
if (gnvs) {
set_sb_aoac(&gnvs->aoac);