printk_foo -> printk(BIOS_FOO, ...)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pci.c b/src/southbridge/intel/i82801gx/i82801gx_pci.c
index d9057cb..c4c22f0 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_pci.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_pci.c
@@ -71,7 +71,7 @@
/* Set the subsystem vendor and device id for mainboard devices */
ops = ops_pci(dev);
if (dev->on_mainboard && ops && ops->set_subsystem) {
- printk_debug("%s subsystem <- %02x/%02x\n",
+ printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
dev_path(dev),
CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
@@ -87,10 +87,10 @@
* this will cause the ROM and APICs not being visible
* anymore.
*/
- printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
+ printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
#else
- printk_debug("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
+ printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
#endif
}
@@ -105,7 +105,7 @@
ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
ctrl |= dev->link[0].bridge_ctrl;
ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
- printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
+ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
/* This is the reason we need our own pci_bus_enable_resources */