diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 8260371..1fbef83 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -1134,7 +1134,7 @@
 #ifdef __PRE_RAM__
 		print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
 #else
-		printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
+		printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
 #endif
 		switch(sysinfo->mem_trained[i]) {
 		case 0: //don't need train
@@ -1152,7 +1152,7 @@
 		print_debug("mem trained failed\n");
 		soft_reset();
 #else
-		printk_debug("mem trained failed\n");
+		printk(BIOS_DEBUG, "mem trained failed\n");
 		hard_reset();
 #endif
 	}
diff --git a/src/northbridge/amd/amdfam10/amdfam10_acpi.c b/src/northbridge/amd/amdfam10/amdfam10_acpi.c
index 0d31c2e..0a35861 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_acpi.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_acpi.c
@@ -60,7 +60,7 @@
 		if (!cpu->enabled) {
 			continue;
 		}
-		printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
+		printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
 		current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id);
 		cpu_index++;
 	}
@@ -89,7 +89,7 @@
 	basek = resk(res->base);
 	sizek = resk(res->size);
 
-	printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
+	printk(BIOS_DEBUG, "set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
 			dev_path(dev), res->index, basek, sizek);
 	/*
 	 * 0-640K must be on node 0
@@ -338,7 +338,7 @@
 		if (!cpu->enabled) {
 			 continue;
 		}
-		printk_debug("ACPI: pstate cpu_index=%02x, node_id=%02x, core_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.core_id);
+		printk(BIOS_DEBUG, "ACPI: pstate cpu_index=%02x, node_id=%02x, core_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.core_id);
 
 		current	  = ( current + 0x0f) & -0x10;
 		ssdt = (acpi_header_t *)current;
diff --git a/src/northbridge/amd/amdfam10/amdfam10_conf.c b/src/northbridge/amd/amdfam10/amdfam10_conf.c
index b52beda..df57804 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_conf.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_conf.c
@@ -779,7 +779,7 @@
 #if 0
 		// FIXME: can we use VGA reg instead?
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-			printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
+			printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
 				__func__, dev_path(dev), link);
 			tempreg |= PCI_IO_BASE_VGA_EN;
 		}
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 7fea9a0..826b83a 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -28,16 +28,16 @@
 static  void print_debug_addr(const char *str, void *val)
 {
 #if CACHE_AS_RAM_ADDRESS_DEBUG == 1
-		printk_debug("------Address debug: %s%x------\n", str, val);
+		printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
 #endif
 }
 
 static void print_debug_pci_dev(u32 dev)
 {
 #if CONFIG_PCI_BUS_SEGN_BITS==0
-	printk_debug("PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
+	printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
 #else
-	printk_debug("PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
+	printk(BIOS_DEBUG, "PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
 #endif
 }
 
@@ -55,7 +55,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		printk_debug(" %04x:%04x\n", (id & 0xffff), (id>>16));
+		printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
 		if(((dev>>12) & 0x07) == 0) {
 			u8 hdr_type;
 			hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
@@ -80,7 +80,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		printk_debug(" %04x:%04x\n", (id & 0xffff), (id>>16));
+		printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
 		if(((dev>>12) & 0x07) == 0) {
 			u8 hdr_type;
 			hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
@@ -103,11 +103,11 @@
 	for(i = start_reg; i < end; i+=4) {
 		u32 val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("\n%04x:",i);
+			printk(BIOS_DEBUG, "\n%04x:",i);
 		}
 		val = pci_read_config32(dev, i);
 		for(j=0;j<4;j++) {
-			printk_debug(" %02x", val & 0xff);
+			printk(BIOS_DEBUG, " %02x", val & 0xff);
 			val >>= 8;
 		}
 	}
@@ -129,10 +129,10 @@
 	for(i = start; i < end; i++) {
 		u32 val;
 		int j;
-		printk_debug("\n%02x:",i);
+		printk(BIOS_DEBUG, "\n%02x:",i);
 		val = pci_read_config32_index_wait(dev, index_reg, i);
 		for(j=0;j<4;j++) {
-			printk_debug(" %02x", val & 0xff);
+			printk(BIOS_DEBUG, " %02x", val & 0xff);
 			val >>= 8;
 		}
 
@@ -160,10 +160,10 @@
 	for(i = 0; i < length; i++) {
 		u32 val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("\n%02x:",i);
+			printk(BIOS_DEBUG, "\n%02x:",i);
 		}
 		val = pci_read_config32_index(dev, index_reg, i|type);
-		printk_debug(" %08x", val);
+		printk(BIOS_DEBUG, " %08x", val);
 	}
 	print_debug("\n");
 }
@@ -231,38 +231,38 @@
 		device = ctrl->spd_addr[i];
 		if (device) {
 			int j;
-			printk_debug("dimm: %02x.0: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
 			for(j = 0; j < 128; j++) {
 				int status;
 				u8 byte;
 				if ((j & 0xf) == 0) {
-					printk_debug("\n%02x: ", j);
+					printk(BIOS_DEBUG, "\n%02x: ", j);
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
 					break;
 				}
 				byte = status & 0xff;
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 			}
 			print_debug("\n");
 		}
 		device = ctrl->spd_addr[i+DIMM_SOCKETS];
 		if (device) {
 			int j;
-			printk_debug("dimm: %02x.1: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
 			for(j = 0; j < 128; j++) {
 				int status;
 				u8 byte;
 				if ((j & 0xf) == 0) {
-					printk_debug("\n%02x: ", j);
+					printk(BIOS_DEBUG, "\n%02x: ", j);
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
 					break;
 				}
 				byte = status & 0xff;
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 			}
 			print_debug("\n");
 		}
@@ -275,7 +275,7 @@
 	for(device = 1; device < 0x80; device++) {
 		int j;
 		if( smbus_read_byte(device, 0) < 0 ) continue;
-		printk_debug("smbus: %02x", device);
+		printk(BIOS_DEBUG, "smbus: %02x", device);
 		for(j = 0; j < 256; j++) {
 			int status;
 			u8 byte;
@@ -284,10 +284,10 @@
 				break;
 			}
 			if ((j & 0xf) == 0) {
-				printk_debug("\n%02x: ",j);
+				printk(BIOS_DEBUG, "\n%02x: ",j);
 			}
 			byte = status & 0xff;
-			printk_debug("%02x ", byte);
+			printk(BIOS_DEBUG, "%02x ", byte);
 		}
 		print_debug("\n");
 	}
@@ -298,14 +298,14 @@
 
 	int i;
 	udelay_tsc(2000);
-	printk_debug("%04x:\n", port);
+	printk(BIOS_DEBUG, "%04x:\n", port);
 	for(i=0;i<256;i++) {
 		u8 val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("%02x:", i);
+			printk(BIOS_DEBUG, "%02x:", i);
 		}
 		val = inb(port);
-		printk_debug(" %02x",val);
+		printk(BIOS_DEBUG, " %02x",val);
 		if ((i & 0x0f) == 0x0f) {
 			print_debug("\n");
 		}
@@ -319,9 +319,9 @@
 	print_debug("dump_mem:");
 	for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (u8)*((u8 *)i));
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
 	}
 	print_debug("\n");
 }
diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c
index f6a196a..fa2e560 100644
--- a/src/northbridge/amd/amdfam10/get_pci1234.c
+++ b/src/northbridge/amd/amdfam10/get_pci1234.c
@@ -75,12 +75,12 @@
 	//here we need to set hcdn
 	//1. hypertransport.c need to record hcdn_reg together with 0xe0, 0xe4, 0xe8, 0xec when are set
 	//2. so at the same time we need update hsdn with hcdn_reg here
-//	printk_debug("sysconf.ht_c_num = %02d\n", sysconf.ht_c_num);
+//	printk(BIOS_DEBUG, "sysconf.ht_c_num = %02d\n", sysconf.ht_c_num);
 
 	for(j=0;j<sysconf.ht_c_num;j++) {
 		u32 dwordx;
 		dwordx = sysconf.ht_c_conf_bus[j];
-//		printk_debug("sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]);
+//		printk(BIOS_DEBUG, "sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]);
 		dwordx &=0xfffffffd; //keep bus num, node_id, link_num, enable bits
 		if((dwordx & 0x7fd) == dword) { //SBLINK
 			sysconf.pci1234[0] = dwordx;
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
index c0650e7..472382c 100644
--- a/src/northbridge/amd/amdfam10/misc_control.c
+++ b/src/northbridge/amd/amdfam10/misc_control.c
@@ -125,7 +125,7 @@
 {
 	u32 cmd;
 
-	printk_debug("NB: Function 3 Misc Control.. ");
+	printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
 
 	/* Disable Machine checks from Invalid Locations.
 	 * This is needed for PC backwards compatibility.
@@ -134,7 +134,7 @@
 	cmd |= (1<<6) | (1<<25);
 	pci_write_config32(dev, 0x44, cmd );
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 4e1ccd6..543d74c 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -83,7 +83,7 @@
 		__f4_dev[i] = get_node_pci(i, 4);
 	}
 	if (!__f1_dev[0]) {
-		printk_err("Cannot find %02x:%02x.1", CONFIG_CBB, CONFIG_CDB);
+		printk(BIOS_ERR, "Cannot find %02x:%02x.1", CONFIG_CBB, CONFIG_CDB);
 		die("Cannot go on\n");
 	}
 }
@@ -568,7 +568,7 @@
 	for (link = 0; link < dev->links; link++) {
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 #if CONFIG_CONSOLE_VGA_MULTI == 1
-			printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
+			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
 				dev->link[link].secondary,dev->link[link].subordinate);
 			/* We need to make sure the vga_pri is under the link */
 			if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
@@ -583,7 +583,7 @@
 	if (link == dev->links)
 		return;
 
-	printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
+	printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
 	set_vga_enable_reg(nodeid, link);
 }
 
@@ -906,9 +906,9 @@
 		mem1 = find_resource(dev, 1|(link<<2));
 		mem2 = find_resource(dev, 2|(link<<2));
 
-		printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+		printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 			mem1->base, mem1->limit, mem1->size, mem1->align);
-		printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+		printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 			mem2->base, mem2->limit, mem2->size, mem2->align);
 
 		/* See if both resources have roughly the same limits */
@@ -934,9 +934,9 @@
 			mem1->base = resource_max(mem1);
 		}
 
-		printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+		printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 			mem1->base, mem1->limit, mem1->size, mem1->align);
-		printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+		printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 			mem2->base, mem2->limit, mem2->size, mem2->align);
 	}
 
@@ -1041,7 +1041,7 @@
 
 		}
 
-//		printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk);
+//		printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk);
 
 		/* split the region to accomodate pci memory space */
 		if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
@@ -1057,7 +1057,7 @@
 					/* Leave some space for ACPI, PIRQ and MP tables */
 						high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
 						high_tables_size = HIGH_TABLES_SIZE * 1024;
-						printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
+						printk(BIOS_DEBUG, "(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
 							     high_tables_base);
 					}
 #endif
@@ -1086,7 +1086,7 @@
 		ram_resource(dev, (idx | i), basek, sizek);
 		idx += 0x10;
 #if CONFIG_WRITE_HIGH_TABLES==1
-		printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
+		printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
 			     i, mmio_basek, basek, limitk);
 		if (i==0 && high_tables_base==0) {
 		/* Leave some space for ACPI, PIRQ and MP tables */
@@ -1144,7 +1144,7 @@
 			if (!dev->link[0].disable_relaxed_ordering) {
 				httc |= HTTC_RSP_PASS_PW;
 			}
-			printk_spew("%s passpw: %s\n",
+			printk(BIOS_SPEW, "%s passpw: %s\n",
 				dev_path(dev),
 				(!dev->link[0].disable_relaxed_ordering)?
 				"enabled":"disabled");
@@ -1247,34 +1247,34 @@
 #if CONFIG_CBB
 	dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
 	if(dev_mc && dev_mc->bus) {
-		printk_debug("%s found", dev_path(dev_mc));
+		printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
 		pci_domain = dev_mc->bus->dev;
 		if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
-			printk_debug("\n%s move to ",dev_path(dev_mc));
+			printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
 			dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
-			printk_debug("%s",dev_path(dev_mc));
+			printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
 
 		} else {
-			printk_debug(" but it is not under pci_domain directly ");
+			printk(BIOS_DEBUG, " but it is not under pci_domain directly ");
 		}
-		printk_debug("\n");
+		printk(BIOS_DEBUG, "\n");
 
 	}
 	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
 	if(!dev_mc) {
 		dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
 		if (dev_mc && dev_mc->bus) {
-			printk_debug("%s found\n", dev_path(dev_mc));
+			printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
 			pci_domain = dev_mc->bus->dev;
 			if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
 				if((pci_domain->links==1) && (pci_domain->link[0].children == dev_mc)) {
-					printk_debug("%s move to ",dev_path(dev_mc));
+					printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
 					dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
-					printk_debug("%s\n",dev_path(dev_mc));
+					printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
 					while(dev_mc){
-						printk_debug("%s move to ",dev_path(dev_mc));
+						printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
 						dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
-						printk_debug("%s\n",dev_path(dev_mc));
+						printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
 						dev_mc = dev_mc->sibling;
 					}
 				}
@@ -1286,7 +1286,7 @@
 
 	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
 	if (!dev_mc) {
-		printk_err("%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
+		printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
 		die("");
 	}
 
@@ -1301,7 +1301,7 @@
 			pci_domain->link[1].link = 1;
 			pci_domain->link[1].dev = pci_domain;
 			pci_domain->link[1].children = 0;
-			printk_debug("%s links increase to %d\n", dev_path(pci_domain), pci_domain->links);
+			printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(pci_domain), pci_domain->links);
 		}
 		pci_domain->link[1].secondary = CONFIG_CBB - 1;
 	}
@@ -1355,7 +1355,7 @@
 					 dev->link[j].dev = dev;
 				}
 				dev->links = linknum;
-				printk_debug("%s links increase to %d\n", dev_path(dev), dev->links);
+				printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(dev), dev->links);
 			}
 		}
 
@@ -1366,7 +1366,7 @@
 			cores_found = (j >> 12) & 3; // dev is func 3
 			if (siblings > 3)
 				cores_found |= (j >> 13) & 4;
-			printk_debug("  %s siblings=%d\n", dev_path(dev), cores_found);
+			printk(BIOS_DEBUG, "  %s siblings=%d\n", dev_path(dev), cores_found);
 		}
 
 		u32 jj;
@@ -1416,7 +1416,7 @@
 					 }
 				}
 	#endif
-				printk_debug("CPU: %s %s\n",
+				printk(BIOS_DEBUG, "CPU: %s %s\n",
 					dev_path(cpu), cpu->enabled?"enabled":"disabled");
 			}
 
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index 21f1e18..4b33fd6 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -20,7 +20,7 @@
 
 static  void print_raminit(const char *strval, u32 val)
 {
-	printk_debug("%s%08x\n", strval, val);
+	printk(BIOS_DEBUG, "%s%08x\n", strval, val);
 }
 
 static  void print_tx(const char *strval, u32 val)
diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c
index b91c922..0d6d743 100644
--- a/src/northbridge/amd/amdfam10/setup_resource_map.c
+++ b/src/northbridge/amd/amdfam10/setup_resource_map.c
@@ -81,7 +81,7 @@
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\n",
+		printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
 			i/4, register_values[i],
 			register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
 			register_values[i+2],
@@ -146,7 +146,7 @@
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\n",
+		printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
 		i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
 #endif
 		switch (register_values[i]) {
diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c
index 249388b..4f73564 100644
--- a/src/northbridge/amd/amdht/comlib.c
+++ b/src/northbridge/amd/amdht/comlib.c
@@ -240,7 +240,7 @@
 
 void ErrorStop(u32 value)
 {
-	printk_debug("Error: %08x ", value);
+	printk(BIOS_DEBUG, "Error: %08x ", value);
 
 }
 
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index 678ba6c..a2b4076 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -84,13 +84,13 @@
 {
 	u8 i;
 
-	printk_debug("AMD_CB_EventNotify()\n");
-	printk_debug(" event class: %02x\n event: %04x\n data: ", evtClass, event);
+	printk(BIOS_DEBUG, "AMD_CB_EventNotify()\n");
+	printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event);
 
 	for (i = 0; i < *pEventData0; i++) {
-		printk_debug(" %02x ", *(pEventData0 + i));
+		printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i));
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 
 }
 
@@ -119,7 +119,7 @@
 	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 	/* If the BUID was adjusted in early_ht we need to do the manual override */
 	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
-		printk_debug("AMD_CB_ManualBUIDSwapList()\n");
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
 		if ((node == 0) && (link == 0)) {	/* BSP SB link */
 			*List = swaplist;
 			return 1;
@@ -170,9 +170,9 @@
 		AMD_CB_EventNotify	// void (*AMD_CB_EventNotify) ();
 	};
 
-	printk_debug("Enter amd_ht_init()\n");
+	printk(BIOS_DEBUG, "Enter amd_ht_init()\n");
 	amdHtInitialize(&ht_wrapper);
-	printk_debug("Exit amd_ht_init()\n");
+	printk(BIOS_DEBUG, "Exit amd_ht_init()\n");
 
 
 }
diff --git a/src/northbridge/amd/amdk8/amdk8_acpi.c b/src/northbridge/amd/amdk8/amdk8_acpi.c
index b5062bd..1257f86 100644
--- a/src/northbridge/amd/amdk8/amdk8_acpi.c
+++ b/src/northbridge/amd/amdk8/amdk8_acpi.c
@@ -81,7 +81,7 @@
 		if (!cpu->enabled) {
 			continue;
 		}
-		printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
+		printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
 		current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id);
 		cpu_index++;
 	}
@@ -110,7 +110,7 @@
 	basek = resk(res->base);
 	sizek = resk(res->size);
 
-	printk_debug("set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n",
+	printk(BIOS_DEBUG, "set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n",
 		     dev_path(dev), res->index, basek, sizek);
 	/*
 	 * 0-640K must be on node 0
diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h
index 7010e80..db2cf8a 100644
--- a/src/northbridge/amd/amdk8/amdk8_f.h
+++ b/src/northbridge/amd/amdk8/amdk8_f.h
@@ -565,7 +565,7 @@
 #ifdef __PRE_RAM__
 		print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n");
 #else
-		printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); 
+		printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); 
 #endif
 		switch(sysinfo->mem_trained[i]) {
 		case 0: //don't need train
@@ -583,7 +583,7 @@
 		print_debug("mem trained failed\r\n");
 		soft_reset();
 #else
-		printk_debug("mem trained failed\n"); 
+		printk(BIOS_DEBUG, "mem trained failed\n"); 
 		hard_reset();
 #endif
 	}
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 45b5a04..66876c2 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -111,7 +111,7 @@
 
 static inline void print_linkn (const char *strval, uint8_t byteval)
 {
-	printk_debug("%s%02x\r\n", strval, byteval);
+	printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval);
 }
 
 static void disable_probes(void)
@@ -1496,7 +1496,7 @@
 		nodes = setup_smp8();
 #endif
 
-	printk_debug("%02x nodes initialized.\r\n", nodes);
+	printk(BIOS_DEBUG, "%02x nodes initialized.\r\n", nodes);
 
 	return nodes;
 }
diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index acfd602..ff2f347 100644
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -10,14 +10,14 @@
 static inline void print_debug_addr(const char *str, void *val)
 {
 #if CACHE_AS_RAM_ADDRESS_DEBUG == 1
-		printk_debug("------Address debug: %s%x------\n", str, val);
+		printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
 #endif
 }
 
 #if 1
 static void print_debug_pci_dev(unsigned dev)
 {
-	printk_debug("PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
+	printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
 }
 
 static void print_pci_devices(void)
@@ -34,7 +34,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		printk_debug(" %04x:%04x\n", (id & 0xffff), (id>>16));
+		printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
 		if(((dev>>12) & 0x07) == 0) {
 			uint8_t hdr_type;
 			hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
@@ -53,10 +53,10 @@
 	for(i = 0; i < 256; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("\n%02x:",i);
+			printk(BIOS_DEBUG, "\n%02x:",i);
 		}
 		val = pci_read_config8(dev, i);
-		printk_debug(" %02x", val);
+		printk(BIOS_DEBUG, " %02x", val);
 	}
 	print_debug("\n");
 }
@@ -72,10 +72,10 @@
 	for(i = 0; i < 0x40; i++) {
 		uint32_t val;
 		int j;
-		printk_debug("\n%02x:",i);
+		printk(BIOS_DEBUG, "\n%02x:",i);
 		val = pci_read_config32_index_wait(dev, index_reg, i);
 		for(j=0;j<4;j++) {
-			printk_debug(" %02x", val & 0xff);
+			printk(BIOS_DEBUG, " %02x", val & 0xff);
 			val >>= 8;
 		}
 
@@ -145,38 +145,38 @@
 		device = ctrl->channel0[i];
 		if (device) {
 			int j;
-			printk_debug("dimm: %02x.0: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
 			for(j = 0; j < 128; j++) {
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					printk_debug("\n%02x: ", j);
+					printk(BIOS_DEBUG, "\n%02x: ", j);
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
 					break;
 				}
 				byte = status & 0xff;
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 			}
 			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
 			int j;
-			printk_debug("dimm: %02x.1: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
 			for(j = 0; j < 128; j++) {
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					printk_debug("\n%02x: ", j);
+					printk(BIOS_DEBUG, "\n%02x: ", j);
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
 					break;
 				}
 				byte = status & 0xff;
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 			}
 			print_debug("\n");
 		}
@@ -189,7 +189,7 @@
 	for(device = 1; device < 0x80; device++) {
 		int j;
 		if( smbus_read_byte(device, 0) < 0 ) continue;
-		printk_debug("smbus: %02x", device);
+		printk(BIOS_DEBUG, "smbus: %02x", device);
 		for(j = 0; j < 256; j++) {
 			int status;
 			unsigned char byte;
@@ -198,10 +198,10 @@
 				break;
 			}
 			if ((j & 0xf) == 0) {
-				printk_debug("\n%02x: ",j);
+				printk(BIOS_DEBUG, "\n%02x: ",j);
 			}
 			byte = status & 0xff;
-			printk_debug("%02x ", byte);
+			printk(BIOS_DEBUG, "%02x ", byte);
 		}
 		print_debug("\n");
 	}
@@ -213,14 +213,14 @@
 
 	int i;
 	udelay(2000);
-	printk_debug("%04x:\n", port);
+	printk(BIOS_DEBUG, "%04x:\n", port);
 	for(i=0;i<256;i++) {
 		uint8_t val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("%02x:", i);
+			printk(BIOS_DEBUG, "%02x:", i);
 		}
 		val = inb(port);
-		printk_debug(" %02x",val);
+		printk(BIOS_DEBUG, " %02x",val);
 		if ((i & 0x0f) == 0x0f) {
 			print_debug("\n");
 		}
@@ -234,9 +234,9 @@
 	print_debug("dump_mem:");
 	for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
 	}
 	print_debug("\n");
  }
diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c
index 8b9a9d4..cf8937a 100644
--- a/src/northbridge/amd/amdk8/exit_from_self.c
+++ b/src/northbridge/amd/amdk8/exit_from_self.c
@@ -43,7 +43,7 @@
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			u32 mnc;
-			printk_spew("ECC enabled\n");
+			printk(BIOS_SPEW, "ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_Width128) {
@@ -52,7 +52,7 @@
 			pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
 		}
 
-		printk_debug("before resume errata #%d\n",
+		printk(BIOS_DEBUG, "before resume errata #%d\n",
 			     (is_post_rev_g) ? 270 : 125);
 		/* 
 		   1. Restore memory controller registers as normal.
@@ -70,7 +70,7 @@
 		enable_lapic();
 		init_timer();
 
-		printk_debug("before exit errata - timer enabled\n");
+		printk(BIOS_DEBUG, "before exit errata - timer enabled\n");
 
 		if (is_post_rev_g) {
 			dcl =
@@ -86,7 +86,7 @@
 
 		udelay(800);
 
-		printk_debug("before exit errata - after mdelay\n");
+		printk(BIOS_DEBUG, "before exit errata - after mdelay\n");
 
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_INIT);
 		dcl &= ~DI_EnDramInit;
@@ -108,7 +108,7 @@
 		pcidev =
 		    0x80000000 | ((((ctrl[i].node_id + 0x18) << 3) | 0x2)
 				  << 8) | 0x90;
-		printk_debug("pcidev is %x\n", pcidev);
+		printk(BIOS_DEBUG, "pcidev is %x\n", pcidev);
 		bitmask = 2;
 		__asm__ __volatile__("pushl %0\n\t"
 				     "movw $0xcf8, %%dx\n\t"
@@ -125,7 +125,7 @@
 				     "q"(bitmask):"edx");
 	}
 
-	printk_debug("after exit errata\n");
+	printk(BIOS_DEBUG, "after exit errata\n");
 
 
 	for (i = 0; i < controllers; i++) {
@@ -136,12 +136,12 @@
 		if (sysinfo->meminfo[i].dimm_mask == 0x00)
 			continue;
 
-		printk_debug("Exiting memory from self refresh: ");
+		printk(BIOS_DEBUG, "Exiting memory from self refresh: ");
 		int loops = 0;
 		do {
 			loops++;
 			if ((loops & 1023) == 0) {
-				printk_debug(".");
+				printk(BIOS_DEBUG, ".");
 			}
 			dcm =
 			    pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
@@ -149,11 +149,11 @@
 			  0) /* || ((dcm & DCM_DramEnabled) == 0) */ );
 
 		if (loops >= TIMEOUT_LOOPS) {
-			printk_debug("timeout with with cntrl[%d]\n", i);
+			printk(BIOS_DEBUG, "timeout with with cntrl[%d]\n", i);
 			continue;
 		}
 
-		printk_debug(" done\n");
+		printk(BIOS_DEBUG, " done\n");
 	}
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
index 737f33b..aa10f3f9 100644
--- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c
+++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
@@ -55,7 +55,7 @@
 		dst_link = (config_map >> 8) & 3;
 		bus_base = (config_map >> 16) & 0xff;
 #if 0
-		printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+		printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
 			dst_node, dst_link, bus_base,
 			reg, config_map);
 #endif
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 4dc302b..2e68618 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -26,7 +26,7 @@
 
 static inline void print_linkn_in (const char *strval, uint8_t byteval)
 {
-	printk_debug("%s%02x\r\n", strval, byteval);
+	printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval);
 }
 
 static uint8_t ht_lookup_capability(device_t dev, uint16_t val)
@@ -127,7 +127,7 @@
 	uint32_t id;
 
 	freq_cap = pci_read_config16(dev, pos);
-	printk_spew("pos=0x%x, unfiltered freq_cap=0x%x\r\n", pos, freq_cap);
+	printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\r\n", pos, freq_cap);
 	freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
 
 	id = pci_read_config32(dev, 0);
@@ -157,8 +157,8 @@
 	#endif
 	}
 
-	printk_spew("pos=0x%x, filtered freq_cap=0x%x\r\n", pos, freq_cap);
-	//printk_spew("capping to 800/600/400/200 MHz\r\n");
+	printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\r\n", pos, freq_cap);
+	//printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\r\n");
 	//freq_cap &= 0x3f;
 	return freq_cap;
 }
@@ -220,14 +220,14 @@
 	int needs_reset;
 	/* Set link width and frequency */
 
-	printk_spew("entering ht_optimize_link\r\n");
+	printk(BIOS_SPEW, "entering ht_optimize_link\r\n");
 	/* Initially assume everything is already optimized and I don't need a reset */
 	needs_reset = 0;
 
 	/* Get the frequency capabilities */
 	freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1));
 	freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2));
-	printk_spew("freq_cap1=0x%x, freq_cap2=0x%x\r\n", freq_cap1, freq_cap2);
+	printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\r\n", freq_cap1, freq_cap2);
 
 	/* Calculate the highest possible frequency */
 	freq = log2(freq_cap1 & freq_cap2);
@@ -236,11 +236,11 @@
 	old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1));
 	old_freq &= 0x0f;
 	needs_reset |= old_freq != freq;
-	printk_spew("dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+	printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
 	old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2));
 	old_freq &= 0x0f;
 	needs_reset |= old_freq != freq;
-	printk_spew("dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+	printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
 
 	/* Set the Calculated link frequency */
 	pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq);
@@ -249,45 +249,45 @@
 	/* Get the width capabilities */
 	width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1));
 	width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2));
-	printk_spew("width_cap1=0x%x, width_cap2=0x%x\r\n", width_cap1, width_cap2);
+	printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\r\n", width_cap1, width_cap2);
 
 	/* Calculate dev1's input width */
 	ln_width1 = link_width_to_pow2[width_cap1 & 7];
 	ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
-	printk_spew("dev1 input ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+	printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
 	if (ln_width1 > ln_width2) {
 		ln_width1 = ln_width2;
 	}
 	width = pow2_to_link_width[ln_width1];
-	printk_spew("dev1 input width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "dev1 input width=0x%x\r\n", width);
 	/* Calculate dev1's output width */
 	ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
 	ln_width2 = link_width_to_pow2[width_cap2 & 7];
-	printk_spew("dev1 output ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+	printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
 	if (ln_width1 > ln_width2) {
 		ln_width1 = ln_width2;
 	}
 	width |= pow2_to_link_width[ln_width1] << 4;
-	printk_spew("dev1 input|output width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "dev1 input|output width=0x%x\r\n", width);
 
 	/* See if I am changing dev1's width */
 	old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1);
 	old_width &= 0x77;
 	needs_reset |= old_width != width;
-	printk_spew("old dev1 input|output width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "old dev1 input|output width=0x%x\r\n", width);
 
 	/* Set dev1's widths */
 	pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width);
 
 	/* Calculate dev2's width */
 	width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
-	printk_spew("dev2 input|output width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "dev2 input|output width=0x%x\r\n", width);
 
 	/* See if I am changing dev2's width */
 	old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1);
 	old_width &= 0x77;
 	needs_reset |= old_width != width;
-	printk_spew("old dev2 input|output width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "old dev2 input|output width=0x%x\r\n", width);
 
 	/* Set dev2's widths */
 	pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width);
@@ -852,16 +852,16 @@
 
 	unsigned link_pair_num = sysinfo->link_pair_num;
 
-	printk_spew("entering optimize_link_incoherent_ht\r\n");
-	printk_spew("sysinfo->link_pair_num=0x%x\r\n", link_pair_num);
+	printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\r\n");
+	printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\r\n", link_pair_num);
 	for(i=0; i< link_pair_num; i++) {
 		struct link_pair_st *link_pair= &sysinfo->link_pair[i];
 		reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
-		printk_spew("after ht_optimize_link for link pair %d, reset_needed=0x%x\r\n", i, reset_needed);
+		printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\r\n", i, reset_needed);
 	}
 
 	reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num);
-	printk_spew("after optimize_link_read_pointers_chain, reset_needed=0x%x\r\n", reset_needed);
+	printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\r\n", reset_needed);
 
 	return reset_needed;
 
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index a1e88aa..1b40eb1 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -112,7 +112,7 @@
 	int needs_reset;
 	struct device *f0_dev, *f2_dev;
 	
-	printk_debug("NB: Function 3 Misc Control.. ");
+	printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
 	needs_reset = 0;
 
 	/* Disable Machine checks from Invalid Locations.
@@ -205,13 +205,13 @@
 		}
 	}
 	else {
-		printk_err("Missing f0 device!\n");
+		printk(BIOS_ERR, "Missing f0 device!\n");
 	}
 	if (needs_reset) {
-		printk_debug("resetting cpu\n");
+		printk(BIOS_DEBUG, "resetting cpu\n");
 		hard_reset();
 	}
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 1dd71de..2ca1444 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -395,14 +395,14 @@
 
 	/* Make certain the resource has actually been set */
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk_err("%s: can't set unassigned resource @%lx %lx\n",
+		printk(BIOS_ERR, "%s: can't set unassigned resource @%lx %lx\n",
 			   __func__, resource->index, resource->flags);
 		return;
 	}
 
 	/* If I have already stored this resource don't worry about it */
 	if (resource->flags & IORESOURCE_STORED) {
-		printk_err("%s: can't set stored resource @%lx %lx\n", __func__,
+		printk(BIOS_ERR, "%s: can't set stored resource @%lx %lx\n", __func__,
 			   resource->index, resource->flags);
 		return;
 	}
@@ -442,7 +442,7 @@
 		limit |= (nodeid & 7);
 
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-			printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
+			printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
 				    __func__, dev_path(dev), link);
 			base |= PCI_IO_BASE_VGA_EN;
 		}
@@ -487,7 +487,7 @@
 	for (link = 0; link < dev->links; link++) {
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 #if CONFIG_CONSOLE_VGA_MULTI == 1
-			printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
+			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
 				dev->link[link].secondary,dev->link[link].subordinate);
 			/* We need to make sure the vga_pri is under the link */
 			if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
@@ -502,12 +502,12 @@
 	if (link == dev->links)
 		return;
 
-	printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
+	printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
 
 	/* allocate a temp resource for the legacy VGA buffer */
 	resource = new_resource(dev, IOINDEX(4, link));
 	if(!resource){
-		printk_debug("VGA: %s out of resources.\n", dev_path(dev));
+		printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev));
 		return;
 	}
 	resource->base = 0xa0000;
@@ -573,10 +573,10 @@
 static void mcf0_control_init(struct device *dev)
 {
 #if 0
-	printk_debug("NB: Function 0 Misc Control.. ");
+	printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. ");
 #endif
 #if 0
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #endif
 }
 
@@ -773,7 +773,7 @@
 	f1_write_config32(0x44 + (node_id << 3),limit - (hole_sizek << 2));
 	dev = __f1_dev[node_id];
 	if (dev == NULL) {
-		printk_err("%s: node %x is NULL!\n", __func__, node_id);
+		printk(BIOS_ERR, "%s: node %x is NULL!\n", __func__, node_id);
 		return;
 	}
 	hoist = pci_read_config32(dev, 0xf0);
@@ -869,9 +869,9 @@
 	mem2 = find_resource(dev, 2);
 
 #if 1
-	printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+	printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 		mem1->base, mem1->limit, mem1->size, mem1->align);
-	printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+	printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 		mem2->base, mem2->limit, mem2->size, mem2->align);
 #endif
 
@@ -899,9 +899,9 @@
 	}
 
 #if 1
-	printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+	printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 		mem1->base, mem1->limit, mem1->size, mem1->align);
-	printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+	printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 		mem2->base, mem2->limit, mem2->size, mem2->align);
 #endif
 
@@ -1005,11 +1005,11 @@
 
 
 #if CONFIG_GFXUMA == 1
-		printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
+		printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
 		if ((uma_memory_base >> 10) < mmio_basek)
-			printk_alert("node %d: UMA memory starts below mmio_basek\n", i);
+			printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i);
 #else
-//		printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
+//		printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
 #endif
 
 		/* See if I need to split the region to accomodate pci memory space */
@@ -1030,7 +1030,7 @@
 						high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
 #endif
 						high_tables_size = HIGH_TABLES_SIZE * 1024;
-						printk_debug(" split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
+						printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
 							     high_tables_base);
 					}
 #endif
@@ -1060,7 +1060,7 @@
 			ram_resource(dev, (idx | i), basek, sizek);
 		idx += 0x10;
 #if CONFIG_WRITE_HIGH_TABLES==1
-		printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
+		printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
 			     i, mmio_basek, basek, limitk);
 		if (i==0 && high_tables_base==0) {
 		/* Leave some space for ACPI, PIRQ and MP tables */
@@ -1101,7 +1101,7 @@
 			if (!dev->link[0].disable_relaxed_ordering) {
 				httc |= HTTC_RSP_PASS_PW;
 			}
-			printk_spew("%s passpw: %s\n",
+			printk(BIOS_SPEW, "%s passpw: %s\n",
 				dev_path(dev),
 				(!dev->link[0].disable_relaxed_ordering)?
 				"enabled":"disabled");
@@ -1207,7 +1207,7 @@
 		if (cpu_dev && cpu_dev->enabled) {
 			j = pci_read_config32(cpu_dev, 0xe8);
 			j = (j >> 12) & 3; // dev is func 3
-			printk_debug("  %s siblings=%d\n", dev_path(cpu_dev), j);
+			printk(BIOS_DEBUG, "  %s siblings=%d\n", dev_path(cpu_dev), j);
 
 			if(nb_cfg_54) {
 				// For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
@@ -1224,7 +1224,7 @@
 				       e0_later_single_core = 0;
 	       			}
 				if(e0_later_single_core) {
-					printk_debug("\tFound Rev E or Rev F later single core\r\n");
+					printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n");
 
 					j=1;
 				}
@@ -1287,7 +1287,7 @@
 						       cpu->path.apic.apic_id += sysconf.apicid_offset;
 					}
 				}
-				printk_debug("CPU: %s %s\n",
+				printk(BIOS_DEBUG, "CPU: %s %s\n",
 					dev_path(cpu), cpu->enabled?"enabled":"disabled");
 			}
 
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 0e27a16..b02e9a0 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -25,7 +25,7 @@
 static void setup_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
-//	printk_debug("setting up resource map....");
+//	printk(BIOS_DEBUG, "setting up resource map....");
 	for (i = 0; i < max; i += 3) {
 		device_t dev;
 		unsigned where;
@@ -37,7 +37,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-//	printk_debug("done.\n");
+//	printk(BIOS_DEBUG, "done.\n");
 }
 
 static int controller_present(const struct mem_controller *ctrl)
@@ -524,10 +524,10 @@
 	int max;
 
 	if (!controller_present(ctrl)) {
-//		printk_debug("No memory controller present\n");
+//		printk(BIOS_DEBUG, "No memory controller present\n");
 		return;
 	}
-	printk_spew("setting up CPU%02x northbridge registers\n", ctrl->node_id);
+	printk(BIOS_SPEW, "setting up CPU%02x northbridge registers\n", ctrl->node_id);
 	max = ARRAY_SIZE(register_values);
 	for (i = 0; i < max; i += 3) {
 		device_t dev;
@@ -540,7 +540,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	printk_spew("done.\n");
+	printk(BIOS_SPEW, "done.\n");
 }
 
 static void hw_enable_ecc(const struct mem_controller *ctrl)
@@ -849,17 +849,17 @@
 	}
 
 	/* Report the amount of memory. */
-	printk_debug("RAM end at 0x%08x kB\n", tom_k);
+	printk(BIOS_DEBUG, "RAM end at 0x%08x kB\n", tom_k);
 
 	/* Now set top of memory */
 	msr_t msr;
 	if (tom_k > (4*1024*1024)) {
-		printk_spew("Handling memory mapped above 4 GB\n");
-		printk_spew("Upper RAM end at 0x%08x kB\n", tom_k);
+		printk(BIOS_SPEW, "Handling memory mapped above 4 GB\n");
+		printk(BIOS_SPEW, "Upper RAM end at 0x%08x kB\n", tom_k);
 		msr.lo = (tom_k & 0x003fffff) << 10;
 		msr.hi = (tom_k & 0xffc00000) >> 22;
 		wrmsr(TOP_MEM2, msr);
-		printk_spew("Correcting memory amount mapped below 4 GB\n");
+		printk(BIOS_SPEW, "Correcting memory amount mapped below 4 GB\n");
 	}
 
 	/* Leave a 64M hole between TOP_MEM and TOP_MEM2
@@ -872,9 +872,9 @@
 		} else
 #endif
 		tom_k = 0x3f0000;
-		printk_spew("Adjusting lower RAM end\n");
+		printk(BIOS_SPEW, "Adjusting lower RAM end\n");
 	}
-	printk_spew("Lower RAM end at 0x%08x kB\n", tom_k);
+	printk(BIOS_SPEW, "Lower RAM end at 0x%08x kB\n", tom_k);
 	msr.lo = (tom_k & 0x003fffff) << 10;
 	msr.hi = (tom_k & 0xffc00000) >> 22;
 	wrmsr(TOP_MEM, msr);
@@ -969,7 +969,7 @@
 		if (is_dual_channel(ctrl)) {
 		/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
 			if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
-//     				printk_debug("8 4GB chip selects cannot be interleaved\n");
+//     				printk(BIOS_DEBUG, "8 4GB chip selects cannot be interleaved\n");
 				return 0;
 			}
 			csbase_inc <<=1;
@@ -979,7 +979,7 @@
 		csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
 		if (is_dual_channel(ctrl)) {
 			if ( (bits==3) && (common_cs_mode > 8)) {
-//				printk_debug("8 cs_mode>8 chip selects cannot be interleaved\n");
+//				printk(BIOS_DEBUG, "8 cs_mode>8 chip selects cannot be interleaved\n");
 				return 0;
 			}
 			csbase_inc <<=1;
@@ -1006,7 +1006,7 @@
 		csbase += csbase_inc;
 	}
 
-	printk_spew("Interleaved\n");
+	printk(BIOS_SPEW, "Interleaved\n");
 
 	/* Return the memory size in K */
 	return common_size << (15 + bits);
@@ -1107,7 +1107,7 @@
 	    read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
 		tom_k = interleave_chip_selects(ctrl);
 	} else {
-		printk_debug("Interleaving disabled\n");
+		printk(BIOS_DEBUG, "Interleaving disabled\n");
 		tom_k = 0;
 	}
 
@@ -1124,7 +1124,7 @@
 
 static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
 {
-	printk_debug("disabling dimm %02x\n", index);
+	printk(BIOS_DEBUG, "disabling dimm %02x\n", index);
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
 	dimm_mask &= ~(1 << index);
@@ -1183,9 +1183,9 @@
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
 
 	if (is_registered(ctrl)) {
-		printk_spew("Registered\n");
+		printk(BIOS_SPEW, "Registered\n");
 	} else {
-		printk_spew("Unbuffered\n");
+		printk(BIOS_SPEW, "Unbuffered\n");
 	}
 
 	return dimm_mask;
@@ -1280,7 +1280,7 @@
 			}
 		}
 	}
-	printk_spew("Enabling dual channel memory\n");
+	printk(BIOS_SPEW, "Enabling dual channel memory\n");
 	uint32_t dcl;
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_32ByteEn;
@@ -1378,7 +1378,7 @@
 	if (!param->cycle_time) {
 		die("min_cycle_time to low");
 	}
-	printk_spew("%s\n", param->name);
+	printk(BIOS_SPEW, "%s\n", param->name);
 	return param;
 }
 
@@ -2073,7 +2073,7 @@
 	long dimm_mask;
 #if 1
 	if (!controller_present(ctrl)) {
-//		printk_debug("No memory controller present\n");
+//		printk(BIOS_DEBUG, "No memory controller present\n");
 		return;
 	}
 #endif
@@ -2081,7 +2081,7 @@
 	activate_spd_rom(ctrl);
 	dimm_mask = spd_detect_dimms(ctrl);
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		printk_debug("No memory for this cpu\n");
+		printk(BIOS_DEBUG, "No memory for this cpu\n");
 		return;
 	}
 	dimm_mask = spd_enable_2channels(ctrl, dimm_mask);
@@ -2105,7 +2105,7 @@
 	return;
  hw_spd_err:
 	/* Unrecoverable error reading SPD data */
-	printk_err("SPD error - reset\n");
+	printk(BIOS_ERR, "SPD error - reset\n");
 	hard_reset();
 	return;
 }
@@ -2171,7 +2171,7 @@
 
 	hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
 
-	printk_spew("Handling memory hole at 0x%08x (default)\n", hole_startk);
+	printk(BIOS_SPEW, "Handling memory hole at 0x%08x (default)\n", hole_startk);
 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
 	/* We need to double check if hole_startk is valid.
 	 * If it is equal to the dram base address in K (base_k),
@@ -2196,7 +2196,7 @@
 			basek_pri = base_k;
 	}
 
-	printk_spew("Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
+	printk(BIOS_SPEW, "Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
 #endif
 	/* Find node number that needs the memory hole configured */
 	for (i=0; i<controllers; i++) {
@@ -2273,7 +2273,7 @@
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			uint32_t mnc;
-			printk_spew("ECC enabled\n");
+			printk(BIOS_SPEW, "ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_128BitEn) {
@@ -2301,17 +2301,17 @@
 			continue;
 		}
 
-		printk_debug("Initializing memory: ");
+		printk(BIOS_DEBUG, "Initializing memory: ");
 		int loops = 0;
 		do {
 			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 			loops++;
 			if ((loops & 1023) == 0) {
-				printk_debug(".");
+				printk(BIOS_DEBUG, ".");
 			}
 		} while(((dcl & DCL_DramInit) != 0) && (loops < TIMEOUT_LOOPS));
 		if (loops >= TIMEOUT_LOOPS) {
-			printk_debug(" failed\n");
+			printk(BIOS_DEBUG, " failed\n");
 			continue;
 		}
 
@@ -2324,7 +2324,7 @@
 			} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
 		}
 
-		printk_debug(" done\n");
+		printk(BIOS_DEBUG, " done\n");
 	}
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 601c035..c38d159 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -34,7 +34,7 @@
 #endif
 
 #if DEBUG_RAM_SETUP
-#define printk_raminit printk_debug
+#define printk_raminit(fmt, arg...) printk(BIOS_DEBUG, fmt, arg)
 #else
 #define printk_raminit(fmt, arg...)
 #endif
@@ -691,7 +691,7 @@
 	}
 	sysinfo->ctrl_present[ctrl->node_id] = 1;
 
-	printk_spew("setting up CPU %02x northbridge registers\n", ctrl->node_id);
+	printk(BIOS_SPEW, "setting up CPU %02x northbridge registers\n", ctrl->node_id);
 	max = ARRAY_SIZE(register_values);
 	for (i = 0; i < max; i += 3) {
 		device_t dev;
@@ -704,7 +704,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	printk_spew("done.\n");
+	printk(BIOS_SPEW, "done.\n");
 }
 
 static int is_dual_channel(const struct mem_controller *ctrl)
@@ -801,7 +801,7 @@
 	if (value <=4 ) value += 8; // add back to 1G to high
 	value += (27-5); // make 128MB to the real lines
 	if ( value != (sz->per_rank)) {
-		printk_err("Bad RANK Size --\n");
+		printk(BIOS_ERR, "Bad RANK Size --\n");
 		goto val_err;
 	}
 
@@ -1041,7 +1041,7 @@
 	}
 
 	/* Report the amount of memory. */
-	printk_debug("RAM end at 0x%08x kB\n", tom_k);
+	printk(BIOS_DEBUG, "RAM end at 0x%08x kB\n", tom_k);
 
 	/* Now set top of memory */
 	msr_t msr;
@@ -1175,7 +1175,7 @@
 		csbase += csbase_inc;
 	}
 
-	printk_debug("Interleaved\n");
+	printk(BIOS_DEBUG, "Interleaved\n");
 
 	/* Return the memory size in K */
 	return common_size << ((27-10) + bits);
@@ -1279,7 +1279,7 @@
 	    CMOS_VLEN_interleave_chip_selects, 1) != 0) {
 		tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
 	} else {
-		printk_debug("Interleaving disabled\n");
+		printk(BIOS_DEBUG, "Interleaving disabled\n");
 		tom_k = 0;
 	}
 
@@ -1297,7 +1297,7 @@
 static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
 			  struct mem_info *meminfo)
 {
-	printk_debug("disabling dimm %02x\n", index);
+	printk(BIOS_DEBUG, "disabling dimm %02x\n", index);
 	if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
@@ -1370,9 +1370,9 @@
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
 
 	if (meminfo->is_registered) {
-		printk_spew("Registered\n");
+		printk(BIOS_SPEW, "Registered\n");
 	} else {
-		printk_spew("Unbuffered\n");
+		printk(BIOS_SPEW, "Unbuffered\n");
 	}
 	return meminfo->dimm_mask;
 }
@@ -1473,7 +1473,7 @@
 		/* Abort if the chips don't support a common CAS latency. */
 		common_cl = spd_read_byte(device0, 18) & spd_read_byte(device1, 18);
 		if (!common_cl) {
-			printk_debug("No common CAS latency supported\n");
+			printk(BIOS_DEBUG, "No common CAS latency supported\n");
 			goto single_channel;
 		} else {
 			printk_raminit("Common CAS latency bitfield: 0x%02x\n", common_cl);
@@ -1495,7 +1495,7 @@
 			}
 		}
 	}
-	printk_spew("Enabling dual channel memory\n");
+	printk(BIOS_SPEW, "Enabling dual channel memory\n");
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_BurstLength32;  /*	32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses
 					32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode	*/
@@ -1514,7 +1514,7 @@
 		if (((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
 			/* mux capable and single dimm in channelB */
 			if (mux_cap) {
-				printk_spew("Enable 64MuxMode & BurstLength32\n");
+				printk(BIOS_SPEW, "Enable 64MuxMode & BurstLength32\n");
 				dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
 				dcm |= DCM_Mode64BitMux;
 				pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
@@ -1529,7 +1529,7 @@
 	} else { /* unmatched dual dimms ? */
 		/* unmatched dual dimms not supported by meminit code. Use single channelA dimm. */
 		meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
-		printk_spew("Unmatched dual dimms. Use single channelA dimm.\n");
+		printk(BIOS_SPEW, "Unmatched dual dimms. Use single channelA dimm.\n");
 	}
 	return meminfo->dimm_mask;
 }
@@ -1610,7 +1610,7 @@
 	if (!param->cycle_time) {
 		die("min_cycle_time to low");
 	}
-	printk_spew("%s\n", param->name);
+	printk(BIOS_SPEW, "%s\n", param->name);
 	return param;
 }
 
@@ -1912,7 +1912,7 @@
 	value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT;
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
 
-	printk_debug("%s\n", result.param->name);
+	printk(BIOS_DEBUG, "%s\n", result.param->name);
 
 	/* Update DRAM Timing Low with our selected cas latency */
 	value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
@@ -1960,7 +1960,7 @@
 
 	if (clocks < DTL_TRC_MIN) {
 #warning We should die here or at least disable this bank.
-		printk_notice("update_dimm_Trc: can't refresh fast enough, "
+		printk(BIOS_NOTICE, "update_dimm_Trc: can't refresh fast enough, "
 			"want %i clocks, can %i clocks\n", clocks, DTL_TRC_MIN);
 		clocks = DTL_TRC_MIN;
 	}
@@ -2057,7 +2057,7 @@
 	}
 	
 	if (clocks > TT_MAX) {
-		printk_info("warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
+		printk(BIOS_INFO, "warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
 		clocks = TT_MAX;
 	}
 
@@ -2372,7 +2372,7 @@
 		if (!(meminfo->dimm_mask & (1 << i))) {
 			if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
 				spd_device = ctrl->channel1[i];
-				printk_debug("set_ecc spd_device: 0x%x\n", spd_device);
+				printk(BIOS_DEBUG, "set_ecc spd_device: 0x%x\n", spd_device);
 			} else {
 				continue;
 			}
@@ -2405,7 +2405,7 @@
 	uint32_t reg;
 
 	if ((val < TT_MIN) || (val > TT_MAX)) {
-		printk_err(str);
+		printk(BIOS_ERR, str);
 		die(" Unknown\n");
 	}
 
@@ -2765,7 +2765,7 @@
 
 		continue;
 	dimm_err:
-		printk_debug("spd_set_dram_timing dimm_err!\n");
+		printk(BIOS_DEBUG, "spd_set_dram_timing dimm_err!\n");
 		if (rc < 0) {
 			return -1;
 		}
@@ -2815,7 +2815,7 @@
 #endif
 	meminfo = &sysinfo->meminfo[ctrl->node_id];
 
-	printk_debug("sdram_set_spd_registers: paramx :%p\n", &paramx);
+	printk(BIOS_DEBUG, "sdram_set_spd_registers: paramx :%p\n", &paramx);
 
 	activate_spd_rom(ctrl);
 	meminfo->dimm_mask = spd_detect_dimms(ctrl);
@@ -2824,7 +2824,7 @@
 
 	if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1)))
 	{
-		printk_debug("No memory for this cpu\n");
+		printk(BIOS_DEBUG, "No memory for this cpu\n");
 		return;
 	}
 	meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo);
@@ -3000,7 +3000,7 @@
 	/* FIXME: How about 32 node machine later? */
 	tsc_t tsc, tsc0[8];
 
-	printk_debug("sdram_enable: tsc0[8]: %p", &tsc0[0]);
+	printk(BIOS_DEBUG, "sdram_enable: tsc0[8]: %p", &tsc0[0]);
 	uint32_t dword;
 #endif
 
@@ -3034,9 +3034,9 @@
 
 	/* lets override the rest of the routine */
 	if (suspend) {
-		printk_debug("Wakeup!\n");
+		printk(BIOS_DEBUG, "Wakeup!\n");
 		exit_from_self(controllers, ctrl, sysinfo);
-		printk_debug("Mem running !\n");
+		printk(BIOS_DEBUG, "Mem running !\n");
 		return;
 	}
 
@@ -3054,7 +3054,7 @@
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			uint32_t mnc;
-			printk_spew("ECC enabled\n");
+			printk(BIOS_SPEW, "ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_Width128) {
@@ -3089,17 +3089,17 @@
 		/* Skip everything if I don't have any memory on this controller */
 		if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-		printk_debug("Initializing memory: ");
+		printk(BIOS_DEBUG, "Initializing memory: ");
 		int loops = 0;
 		do {
 			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 			loops++;
 			if ((loops & 1023) == 0) {
-				printk_debug(".");
+				printk(BIOS_DEBUG, ".");
 			}
 		} while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS));
 		if (loops >= TIMEOUT_LOOPS) {
-			printk_debug(" failed\n");
+			printk(BIOS_DEBUG, " failed\n");
 			continue;
 		}
 
@@ -3127,7 +3127,7 @@
 			print_debug_dqs_tsc("     dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
 		}
 #endif
-		printk_debug(" done\n");
+		printk(BIOS_DEBUG, " done\n");
 	}
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 6ff7a95..89ccf90 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -25,7 +25,7 @@
 {
 #if DQS_TRAIN_DEBUG > 0
 	if(DQS_TRAIN_DEBUG > level) {
-		printk_debug("%s%x\r\n", str, val);
+		printk(BIOS_DEBUG, "%s%x\r\n", str, val);
 	}
 #endif
 }
@@ -34,7 +34,7 @@
 {
 #if DQS_TRAIN_DEBUG > 0
 	if(DQS_TRAIN_DEBUG > level) {
-		printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2);
+		printk(BIOS_DEBUG, "%s%08x%s%08x\r\n", str, val, str2, val2);
 	}
 #endif
 }
@@ -43,14 +43,14 @@
 {
 #if DQS_TRAIN_DEBUG > 0
 	if(DQS_TRAIN_DEBUG > level) {
-		printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+		printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2);
 	}
 #endif
 }
 
 static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2)
 {
-	printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+	printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2);
 
 }
 
@@ -854,7 +854,7 @@
 
 #if CONFIG_MEM_TRAIN_SEQ != 1
 	/* We need tidy output for type 1 */
-	printk_debug(" CTLRMaxDelay=%02x\n", CTLRMaxDelay);
+	printk(BIOS_DEBUG, " CTLRMaxDelay=%02x\n", CTLRMaxDelay);
 #endif
 
 	return (CTLRMaxDelay==0xae)?1:0;
@@ -1130,7 +1130,7 @@
 
 	print_debug_dqs("\t\t\tTrainDQSPos begin ", 0, 3);
 
-	printk_debug("TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW);
+	printk(BIOS_DEBUG, "TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW);
 
 	for(DQSDelay=0; DQSDelay<48; DQSDelay++) {
 		MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS)
@@ -1403,7 +1403,7 @@
 
 	print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0);
 
-	printk_debug("TrainDQSRdWrPos: buf_a:%p\n", buf_a);
+	printk(BIOS_DEBUG, "TrainDQSRdWrPos: buf_a:%p\n", buf_a);
 
 	Errors = 0;
 	channel = 0;
@@ -1537,7 +1537,7 @@
 {
 	print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0);
 	if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) {
-		printk_err("\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id);
+		printk(BIOS_ERR, "\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id);
 		return 1;
 	}
 	else {
@@ -1700,7 +1700,7 @@
 		}
 		sizek = 1 << align;
 #if CONFIG_MEM_TRAIN_SEQ != 1
-		printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n",
+		printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n",
 			reg, range_startk >>10, sizek >> 10,
 			(type==MTRR_TYPE_UNCACHEABLE)?"UC":
 			    ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
@@ -1895,7 +1895,7 @@
 {
 	int pos = 0;
 	u32 reg;
-	printk_debug("DQS SAVE NVRAM: %x\n", dev);
+	printk(BIOS_DEBUG, "DQS SAVE NVRAM: %x\n", dev);
 	pos = dqs_save_MC_NVRAM_ch(dev, 0, pos);
 	pos = dqs_save_MC_NVRAM_ch(dev, 1, pos);
 	/* save the maxasync lat here */
@@ -1908,7 +1908,7 @@
 	int pos = 0;
 	u32 reg;
 
-	printk_debug("DQS RESTORE FROM NVRAM: %x\n", dev);
+	printk(BIOS_DEBUG, "DQS RESTORE FROM NVRAM: %x\n", dev);
 	pos = dqs_load_MC_NVRAM_ch(dev, 0, pos);
 	pos = dqs_load_MC_NVRAM_ch(dev, 1, pos);
 	/* load the maxasync lat here */
@@ -1950,9 +1950,9 @@
 		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-		printk_debug("DQS Training:RcvrEn:Pass1: %02x\n", i);
+		printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i);
 		if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out;
-       		printk_debug(" done\r\n");
+       		printk(BIOS_DEBUG, " done\r\n");
 	}
 
 	tsc[1] = rdtsc();
@@ -1968,9 +1968,9 @@
 		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-		printk_debug("DQS Training:DQSPos: %02x\n", i);
+		printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i);
 		if(train_DqsPos(ctrl+i, sysinfo)) goto out;
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 	}
 
 	tsc[3] = rdtsc();
@@ -1981,9 +1981,9 @@
 		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-		printk_debug("DQS Training:RcvrEn:Pass2: %02x\n", i);
+		printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i);
 		if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 		sysinfo->mem_trained[i]=1;
 		dqs_save_MC_NVRAM((ctrl+i)->f2);
 	}
@@ -2025,7 +2025,7 @@
 	if(v) {
 		tsc[0] = rdtsc();
 
-		printk_debug("set DQS timing:RcvrEn:Pass1: %02x\n", i);
+		printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass1: %02x\n", i);
 	}
 	if(train_DqsRcvrEn(ctrl, 1,  sysinfo)) {
 		sysinfo->mem_trained[i]=0x81; //
@@ -2033,9 +2033,9 @@
 	}
 
 	if(v) {
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 		tsc[1] = rdtsc();
-		printk_debug("set DQS timing:DQSPos: %02x\n", i);
+		printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x\n", i);
 	}
 
 	if(train_DqsPos(ctrl, sysinfo)) {
@@ -2044,10 +2044,10 @@
 	}
 
 	if(v) {
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 		tsc[2] = rdtsc();
 
-		printk_debug("set DQS timing:RcvrEn:Pass2: %02x\n", i);
+		printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i);
 	}
 	if(train_DqsRcvrEn(ctrl, 2,  sysinfo)){
 		sysinfo->mem_trained[i]=0x83; //
@@ -2055,7 +2055,7 @@
 	}
 
 	if(v) {
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 
 		tsc[3] = rdtsc();
 	}
@@ -2106,7 +2106,7 @@
 	#endif
 		set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
 	#if CONFIG_AP_CODE_IN_CAR == 0
-		printk_debug("CODE IN ROM AND RUN ON NODE: %02x\n", nodeid);
+		printk(BIOS_DEBUG, "CODE IN ROM AND RUN ON NODE: %02x\n", nodeid);
 		train_ram(nodeid, sysinfo, sysinfox);
 	#else
 		/* Can copy dqs_timing to ap cache and run from cache?
diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c
index 728ba88..cd7b3b5 100644
--- a/src/northbridge/amd/amdk8/setup_resource_map.c
+++ b/src/northbridge/amd/amdk8/setup_resource_map.c
@@ -49,7 +49,7 @@
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
+		printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n",
 			i>>2, register_values[i],
 			register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
 			register_values[i+2],
@@ -129,7 +129,7 @@
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
+		printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n",
 			i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
 #endif
 		switch (register_values[i]) {
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 22e9902..ec767fa 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -556,7 +556,7 @@
 			base  += NextBase;
 			limit += NextBase;
 			DramSelBaseAddr += NextBase;
-			printk_debug(" Node: %02x  base: %02x  limit: %02x  BottomIO: %02x\n", Node, base, limit, BottomIO);
+			printk(BIOS_DEBUG, " Node: %02x  base: %02x  limit: %02x  BottomIO: %02x\n", Node, base, limit, BottomIO);
 
 			if (_MemHoleRemap) {
 				if ((base < BottomIO) && (limit >= BottomIO)) {
@@ -633,7 +633,7 @@
 		devx = pDCTstat->dev_map;
 
 		if (pDCTstat->NodePresent) {
-		printk_debug(" Copy dram map from Node 0 to Node %02x \n", Node);
+		printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x \n", Node);
 			reg = 0x40;		/*Dram Base 0*/
 			do {
 				val = Get_NB32(dev, reg);
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 7f8b896..9dfccd9 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -69,7 +69,7 @@
 {
 #if DQS_TRAIN_DEBUG > 0
 	if (DQS_TRAIN_DEBUG >= level) {
-		printk_debug("%s%x\n", str, val);
+		printk(BIOS_DEBUG, "%s%x\n", str, val);
 	}
 #endif
 }
@@ -78,7 +78,7 @@
 {
 #if DQS_TRAIN_DEBUG > 0
 	if (DQS_TRAIN_DEBUG >= level) {
-		printk_debug("%s%08x%s%08x\n", str, val, str2, val2);
+		printk(BIOS_DEBUG, "%s%08x%s%08x\n", str, val, str2, val2);
 	}
 #endif
 }
diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index 4eb02c7..1b0214d 100644
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -42,11 +42,11 @@
 
 static void northbridge_init(device_t dev) 
 {
-	printk_debug("northbridge: %s()\n", __func__);
+	printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
 	
 	optimize_xbus(dev);
 	enable_shadow(dev);
-	printk_spew("Calling enable_cache()\n");
+	printk(BIOS_SPEW, "Calling enable_cache()\n");
 	enable_cache();
 }
 
@@ -140,10 +140,10 @@
 		*bcdramtop = ((tomk << 10) - 1);
 		*mcgbaseadd = (tomk >> 9);
 
-		printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
-		printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
+		printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
+		printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
 
-		printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
+		printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
 
 		/* Compute the top of Low memory */
 		tolmk = pci_tolm >> 10;
@@ -176,7 +176,7 @@
 
 static void cpu_bus_init(device_t dev)
 {
-	printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
+	printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
 	initialize_cpus(&dev->link[0]);
 }
 
@@ -194,18 +194,18 @@
 
 static void enable_dev(struct device *dev)
 {
-        printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
+        printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
-        	printk_spew("DEVICE_PATH_PCI_DOMAIN\n");
+        	printk(BIOS_SPEW, "DEVICE_PATH_PCI_DOMAIN\n");
                 dev->ops = &pci_domain_ops;
 		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
-        	printk_spew("DEVICE_PATH_APIC_CLUSTER\n");
+        	printk(BIOS_SPEW, "DEVICE_PATH_APIC_CLUSTER\n");
                 dev->ops = &cpu_bus_ops;
         } else {
-        	printk_spew("device path type %d\n",dev->path.type);
+        	printk(BIOS_SPEW, "device path type %d\n",dev->path.type);
 	}
 }
 
diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c
index 53a9053..cbb4e65 100644
--- a/src/northbridge/amd/gx2/chipsetinit.c
+++ b/src/northbridge/amd/gx2/chipsetinit.c
@@ -87,7 +87,7 @@
 	msr_t msr;
 	msr = rdmsr(GLIU_SB_GLD_MSR_CAP);
 	msr.lo >>= 20;
-	printk_debug("is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf);
+	printk(BIOS_DEBUG, "is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf);
 	return ((msr.lo&0xf) == 5);
 }
 /* ***************************************************************************/
@@ -205,10 +205,10 @@
 	int i;
 	int numEnabled = 0;
 
-	printk_debug("ChipsetFlashSetup++\n");
+	printk(BIOS_DEBUG, "ChipsetFlashSetup++\n");
 	for (i = 0; i < FlashInitTableLen; i++) {
 		if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
-			printk_debug("Enable CS%d\n", i);
+			printk(BIOS_DEBUG, "Enable CS%d\n", i);
 			/* we need to configure the memory/IO mask */
 			msr = rdmsr(FlashPort[i]);
 			msr.hi = 0;	/* start with the "enabled" bit clear */
@@ -221,13 +221,13 @@
 			else
 				msr.hi &= ~0x00000004;
 			msr.hi |= FlashInitTable[i].fMask;
-			printk_debug("WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
+			printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
 			wrmsr(FlashPort[i], msr);
 
 			/* now write-enable the device */
 			msr = rdmsr(MDD_NORF_CNTRL);
 			msr.lo |= (1 << i);
-			printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
+			printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
 			wrmsr(MDD_NORF_CNTRL, msr);
 
 			/* update the number enabled */
@@ -239,10 +239,10 @@
 	if (0 != numEnabled) {
 		msr = rdmsr(MDD_PIN_OPT);
 		msr.lo &= ~1; /* PIN_OPT_IDE */
-		printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);
 		wrmsr(MDD_PIN_OPT, msr);
 	}
-	printk_debug("ChipsetFlashSetup--\n");
+	printk(BIOS_DEBUG, "ChipsetFlashSetup--\n");
 
 }
 
@@ -359,7 +359,7 @@
 
 
 	/*  Flash Setup*/
-	printk_err("%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? " " : "NOT");
+	printk(BIOS_ERR, "%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? " " : "NOT");
 	if (nb->setupflash)
 		ChipsetFlashSetup();
 
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index b20d3d7..274277d 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -32,7 +32,7 @@
 	unsigned short dimm;
 
 	msr = rdmsr(0x20000018);
-	printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo);
 
 	/* dimm 0 */
 	dimm = msr.hi;
@@ -47,7 +47,7 @@
 	if ((dimm & 7) != 7)
 		sizem += (1 << ((dimm >> 12)-1)) * 8;
 
-	printk_debug("sizeram: sizem 0x%x\n", sizem);
+	printk(BIOS_DEBUG, "sizeram: sizem 0x%x\n", sizem);
 	return sizem;
 }
 
@@ -127,7 +127,7 @@
 	/* Set up IRQ steering */
 	uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
 
-	printk_debug("%s(%08X [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
+	printk(BIOS_DEBUG, "%s(%08X [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
 
 	/* The IRQ steering values (in hex) are effectively dcba, where:
 	 *    <a> represents the IRQ for INTA, 
@@ -160,7 +160,7 @@
 	int sizekbytes, sizereg;
 
 	sizekbytes = sizeram() * 1024;
-	printk_debug("setup_gx2_cache: enable for %d KB\n", sizekbytes);
+	printk(BIOS_DEBUG, "setup_gx2_cache: enable for %d KB\n", sizekbytes);
 	/* build up the rconf word. */
 	/* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
 	/* set romrp */
@@ -181,7 +181,7 @@
 	val |= RAM_PROPERTIES;
 	msr.lo = val;
 	msr.hi = (val >> 32);
-	printk_debug("msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
 	wrmsr(CPU_RCONF_DEFAULT, msr);
 
 	enable_cache();
@@ -214,7 +214,7 @@
 
 #if 0
 	/* This has already been done elsewhere */
-	printk_debug("size_kb 0x%x, membytes 0x%x\n", size_kb, membytes);
+	printk(BIOS_DEBUG, "size_kb 0x%x, membytes 0x%x\n", size_kb, membytes);
 	msr.hi = 0x20000000 | membytes>>24;
 	msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
 	wrmsr(0x10000028, msr);
@@ -224,9 +224,9 @@
 #endif
 #if 0
 	msr = rdmsr(0x10000028);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
 	msr = rdmsr(0x40000029);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
 #endif
 #if 1
 	/* fixme: SMM MSR 0x10000026 and 0x400000023 */
@@ -240,7 +240,7 @@
 	/* calculate the PBASE and PMASK fields */
 	tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20  == left 8 */
 	tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
 	msr.hi = tmp;
 	msr.lo = tmp2;
 	wrmsr(0x10000026, msr);
@@ -251,14 +251,14 @@
 	msr.lo = 0x400fffc0;
 	wrmsr(0x10000026, msr);
 	msr = rdmsr(0x10000026);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
 #endif
 #if 0
 	msr.hi = 0x22fffc02;
 	msr.lo = 0x10ffbf00;
 	wrmsr(0x1808, msr);
 	msr = rdmsr(0x1808);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
 #endif
 #if 0	// SDG - don't do this
 	/* now do the default MSR values */
@@ -266,7 +266,7 @@
 		msr_t msr;
 		wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr);	// MSR - see table above
 		msr = rdmsr(msr_defaults[i].msr_no);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
 	}
 #endif
 }
@@ -281,7 +281,7 @@
 	unsigned long m;
 
 	struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
-	printk_debug("northbridge: %s()\n", __func__);
+	printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
 	
 	enable_shadow(dev);
 	irq_init_steering(dev, nb->irqmap);
@@ -429,10 +429,10 @@
 		*bcdramtop = ((tomk << 10) - 1);
 		*mcgbaseadd = (tomk >> 9);
 
-		printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
-		printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
+		printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
+		printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
 
-		printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
+		printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
 
 		/* Compute the top of Low memory */
 		tolmk = pci_tolm >> 10;
@@ -483,7 +483,7 @@
 
 static void enable_dev(struct device *dev)
 {
-	printk_debug("gx2 north: enable_dev\n");
+	printk(BIOS_DEBUG, "gx2 north: enable_dev\n");
 	void northbridgeinit(void);
 	void chipsetinit(struct northbridge_amd_gx2_config *nb);
 	void do_vsmbios(void);
@@ -492,7 +492,7 @@
 		struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
 		extern void cpubug(void);
 		u32 tomk;
-		printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
+		printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n");
 		/* cpubug MUST be called before setup_gx2(), so we force the issue here */
 		northbridgeinit();
 		cpubug();	
@@ -510,10 +510,10 @@
 #endif
 		ram_resource(dev, 0, 0, tomk);
         } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
-		printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
+		printk(BIOS_DEBUG, "DEVICE_PATH_APIC_CLUSTER\n");
                 dev->ops = &cpu_bus_ops;
         }
-	printk_debug("gx2 north: end enable_dev\n");
+	printk(BIOS_DEBUG, "gx2 north: end enable_dev\n");
 }
 
 struct chip_operations northbridge_amd_gx2_ops = {
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index 995c1f3..4914665 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -112,10 +112,10 @@
 	msr.lo = gl->lo;
 	msr.hi = gl->hi;
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk_debug("%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 	/* they do this, so we do this */
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
 static void
@@ -147,7 +147,7 @@
 	 * system. We will adjust for SMM and DMM now and Frame Buffer later.
 	 */
 	sizembytes = sizeram();
-	printk_debug("%s: enable for %dm bytes\n", __func__, sizembytes);
+	printk(BIOS_DEBUG, "%s: enable for %dm bytes\n", __func__, sizembytes);
 	sizebytes = sizembytes << 20;
 
 	sizebytes -= SMM_SIZE*1024 +1;
@@ -164,7 +164,7 @@
 	msr.lo = sizebytes;
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, 
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, 
 				gl->desc_name, msr.hi, msr.lo);
 	
 }
@@ -177,11 +177,11 @@
 	if (! havedmi)
 		return;
 
-	printk_debug("%s: %d bytes\n", __func__, sizebytes);
+	printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
 
 	sizebytes -= DMM_SIZE*1024;
 	offset = sizebytes - DMM_OFFSET;
-	printk_debug("%s: offset is 0x%08x\n", __func__, offset);
+	printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, offset);
 	offset >>= 12;
 	msr.hi = (gl->hi) | (offset << 8);
 	/* I don't think this is needed */
@@ -192,7 +192,7 @@
 	
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 	
 }
 static void
@@ -202,7 +202,7 @@
 	if (! havedmi)
 		return;
 
-	printk_debug("%s:\n", __func__ );
+	printk(BIOS_DEBUG, "%s:\n", __func__ );
 
 	msr.hi = gl->hi;
 	/* I don't think this is needed */
@@ -210,12 +210,12 @@
 	msr.hi |= (DMM_OFFSET >> 24);
 	msr.lo = DMM_OFFSET << 8;
 	/* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */
-	printk_err("%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__);
+	printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__);
 	msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
 	
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 static void
 SMMGL0Init(struct gliutable *gl) {
@@ -228,10 +228,10 @@
 	if (havedmi)
 		sizebytes -= DMM_SIZE * 1024;
 
-	printk_debug("%s: %d bytes\n", __func__, sizebytes);
+	printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
 
 	offset = sizebytes - SMM_OFFSET;
-	printk_debug("%s: offset is 0x%08x\n", __func__, offset);
+	printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, offset);
 	offset >>= 12;
 
 	msr.hi = offset << 8;
@@ -242,12 +242,12 @@
 	
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 static void
 SMMGL1Init(struct gliutable *gl) {
 	msr_t msr;
-	printk_debug("%s:\n", __func__ );
+	printk(BIOS_DEBUG, "%s:\n", __func__ );
 
 	msr.hi = gl->hi;
 	/* I don't think this is needed */
@@ -258,7 +258,7 @@
 	
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
 static void
@@ -350,7 +350,7 @@
 		/* So we need a high page aligned addresss (pah) and low page aligned address (pal)
 		 * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
 		 */
-		printk_debug("GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
+		printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
 		pah = ((msr.hi &0xff) << 12) | ((msr.lo >> 20) & 0xfff);
 		/* we have the page address. Now make it a page-aligned address */
 		pah <<= 12;
@@ -359,7 +359,7 @@
 		msr.hi =  pah;
 		msr.lo =  pal;
 		msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET;
-		printk_debug("GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
+		printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
 		msrnum = GLPCI_RC1;
 		wrmsr(msrnum, msr);
 	}
@@ -507,10 +507,10 @@
 
 	for(i = 0; gating->msrnum != 0xffffffff; i++) {
 		msr = rdmsr(gating->msrnum);
-		printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo);
 		msr.hi |= gating->msr.hi;
 		msr.lo |= gating->msr.lo;
-		printk_debug("%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__, 
+		printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__, 
 			gating->msrnum, msr.hi, msr.lo);
 		wrmsr(gating->msrnum, msr);	// MSR - See the table above
 		gating +=1;
@@ -526,11 +526,11 @@
 
 	for(i = 0; prio->msrnum != 0xffffffff; i++) {
 		msr = rdmsr(prio->msrnum);
-		printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo);
 		msr.hi |= prio->msr.hi;
 		msr.lo &= ~0xfff;
 		msr.lo |= prio->msr.lo;
-		printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__, 
+		printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__, 
 			prio->msrnum, msr.hi, msr.lo);
 		wrmsr(prio->msrnum, msr);	// MSR - See the table above
 		prio +=1;
@@ -772,7 +772,7 @@
 {
 	msr_t msr;
 	int i;
-	printk_debug("Enter %s\n", __func__);
+	printk(BIOS_DEBUG, "Enter %s\n", __func__);
 
 	for(i = 0; gliutables[i]; i++)
 		GLIUInit(gliutables[i]);
@@ -803,6 +803,6 @@
 	ClockGatingInit();
 	__asm__("FINIT\n");
 	/* CPUBugsFix -- called elsewhere */
-	printk_debug("Exit %s\n", __func__);
+	printk(BIOS_DEBUG, "Exit %s\n", __func__);
 }
 
diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c
index 1312d78..85e6a45 100644
--- a/src/northbridge/amd/lx/grphinit.c
+++ b/src/northbridge/amd/lx/grphinit.c
@@ -70,7 +70,7 @@
 	uint16_t wClassIndex, wData, res;
 
 	/* SoftVG initialization */
-	printk_debug("Graphics init...\n");
+	printk(BIOS_DEBUG, "Graphics init...\n");
    
 	geodelx_vga_msr_init();
    
@@ -99,5 +99,5 @@
 	vrWrite(wClassIndex, wData);
 
 	res = vrRead(wClassIndex);
-	printk_debug("VRC_VG value: 0x%04x\n", res);
+	printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res);
 }
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 935d1f2..5c97649 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -173,96 +173,96 @@
 		MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
 	};
 
-	printk_debug("---------- CPU ------------\n");
+	printk(BIOS_DEBUG, "---------- CPU ------------\n");
 
 	for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
 		msr = rdmsr(cpu_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
 			     cpu_msr_defs[i], msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- GLIU 0 ------------\n");
+	printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n");
 
 	for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
 		msr = rdmsr(gliu0_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
 			     gliu0_msr_defs[i], msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- GLIU 1 ------------\n");
+	printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n");
 
 	for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
 		msr = rdmsr(gliu1_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
 			     gliu1_msr_defs[i], msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- RCONF ------------\n");
+	printk(BIOS_DEBUG, "---------- RCONF ------------\n");
 
 	for (i = 0; rconf_msr[i] != GL_END; i++) {
 		msr = rdmsr(rconf_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
 			     msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- VARIA ------------\n");
+	printk(BIOS_DEBUG, "---------- VARIA ------------\n");
 	msr = rdmsr(0x51300010);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
 		     msr.lo);
 
 	msr = rdmsr(0x51400015);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
 		     msr.lo);
 
-	printk_debug("---------- DIVIL IRQ ------------\n");
+	printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n");
 	msr = rdmsr(MDD_IRQM_YLOW);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
 		     msr.lo);
 	msr = rdmsr(MDD_IRQM_YHIGH);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
 		     msr.hi, msr.lo);
 	msr = rdmsr(MDD_IRQM_ZLOW);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
 		     msr.lo);
 	msr = rdmsr(MDD_IRQM_ZHIGH);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
 		     msr.hi, msr.lo);
 
-	printk_debug("---------- PCI ------------\n");
+	printk(BIOS_DEBUG, "---------- PCI ------------\n");
 
 	for (i = 0; pci_msr[i] != GL_END; i++) {
 		msr = rdmsr(pci_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
 			     msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- LPC/UART DMA ------------\n");
+	printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n");
 
 	for (i = 0; dma_msr[i] != GL_END; i++) {
 		msr = rdmsr(dma_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
 			     msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- CS5536 ------------\n");
+	printk(BIOS_DEBUG, "---------- CS5536 ------------\n");
 
 	for (i = 0; cs5536_msr[i] != GL_END; i++) {
 		msr = rdmsr(cs5536_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
 			     msr.hi, msr.lo);
 	}
 
 	iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n",
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
 		     GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
 	iol = inl(GPIOL_EVENTS_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n",
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
 		     GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
 	iol = inl(GPIOL_INPUT_INVERT_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n",
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
 		     GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
 	iol = inl(GPIO_MAPPER_X);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
 		     iol);
 #endif				//CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
 }
@@ -278,7 +278,7 @@
 
 	/* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
 	msr = rdmsr(MC_CF07_DATA);
-	printk_debug("sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
 
 	/* dimm 0 */
 	dimm = msr.hi;
@@ -294,7 +294,7 @@
 		sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
 	}
 
-	printk_debug("sizeram: sizem 0x%xMB\n", sizem);
+	printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem);
 	return sizem;
 }
 
@@ -306,7 +306,7 @@
 {
 	//msr_t msr;
 
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	enable_shadow(dev);
 	/*
@@ -317,8 +317,8 @@
 	//msr.hi |= 0x3;
 	//msr.lo |= 0x30000;
 
-	//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
-	//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
+	//printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
+	//printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
 }
 
 void northbridge_set_resources(struct device *dev)
@@ -340,8 +340,7 @@
 		struct bus *bus;
 		bus = &dev->link[link];
 		if (bus->children) {
-			printk_debug
-			    ("my_dev_set_resources: assign_resources %d\n",
+			printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n",
 			     bus);
 			assign_resources(bus);
 		}
@@ -406,7 +405,7 @@
 	u32 tomk;
 	device_t mc_dev;
 
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	mc_dev = dev->link[0].children;
 	if (mc_dev) {
@@ -430,7 +429,7 @@
 static void pci_domain_enable(device_t dev)
 {
 
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	// do this here for now -- this chip really breaks our device model
 	northbridge_init_early();
@@ -439,12 +438,12 @@
 
 	setup_realmode_idt();
 
-	printk_debug("Before VSA:\n");
+	printk(BIOS_DEBUG, "Before VSA:\n");
 	// print_conf();
 
 	do_vsmbios();		// do the magic stuff here, so prepare your tambourine ;)
 
-	printk_debug("After VSA:\n");
+	printk(BIOS_DEBUG, "After VSA:\n");
 	// print_conf();
 
 	graphics_init();
@@ -461,7 +460,7 @@
 
 static void cpu_bus_init(device_t dev)
 {
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	initialize_cpus(&dev->link[0]);
 }
@@ -480,7 +479,7 @@
 
 static void enable_dev(struct device *dev)
 {
-	printk_spew(">> Entering northbridge.c: %s with path %d\n",
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n",
 		    __func__, dev->path.type);
 
 	/* Set the operations if it is a special bus type */
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index 4336e82..54cc057 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -107,7 +107,7 @@
 	msr.lo = gl->lo;
 	msr.hi = gl->hi;
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);	// GX3
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);	// GX3
 }
 
 static void ShadowInit(struct gliutable *gl)
@@ -131,11 +131,11 @@
 	 * system. We will adjust for SMM now and Frame Buffer later.
 	 */
 	sizembytes = sizeram();
-	printk_debug("%s: enable for %dMBytes\n", __func__, sizembytes);
+	printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", __func__, sizembytes);
 	sizebytes = sizembytes << 20;
 
 	sizebytes -= ((SMM_SIZE * 1024) + 1);
-	printk_debug("usable RAM: %d bytes\n", sizebytes);
+	printk(BIOS_DEBUG, "usable RAM: %d bytes\n", sizebytes);
 
 	/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo
 	   The top 8 bits go into 0-7 of msr.hi. */
@@ -147,7 +147,7 @@
 	msr.lo = sizebytes;
 
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 		     gl->desc_name, msr.hi, msr.lo);
 }
 
@@ -159,12 +159,12 @@
 
 	sizebytes -= (SMM_SIZE * 1024);
 
-	printk_debug("%s: %d bytes\n", __func__, sizebytes);
+	printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
 
 	/* calculate the Two's complement offset */
 	offset = sizebytes - SMM_OFFSET;
 	offset = (offset >> 12) & 0x000fffff;
-	printk_debug("%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
+	printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
 
 	msr.hi = offset << 8 | gl->hi;
 	msr.hi |= SMM_OFFSET >> 24;
@@ -173,14 +173,14 @@
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 		     gl->desc_name, msr.hi, msr.lo);
 }
 
 static void SMMGL1Init(struct gliutable *gl)
 {
 	msr_t msr;
-	printk_debug("%s:\n", __func__);
+	printk(BIOS_DEBUG, "%s:\n", __func__);
 
 	msr.hi = gl->hi;
 	/* I don't think this is needed */
@@ -190,7 +190,7 @@
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 		     gl->desc_name, msr.hi, msr.lo);
 }
 
@@ -290,7 +290,7 @@
 		msr.lo |=
 		    GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET |
 		    GLPCI_RC_LOWER_WC_SET;
-		printk_debug("GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n",
+		printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n",
 			     msr.lo, msr.hi);
 		msrnum = GLPCI_RC1;
 		wrmsr(msrnum, msr);
@@ -304,7 +304,7 @@
 	      (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
 	msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
 	msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
-	printk_debug("GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo,
+	printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo,
 		     msr.hi);
 	msrnum = GLPCI_RC2;
 	wrmsr(msrnum, msr);
@@ -435,7 +435,7 @@
 		msr = rdmsr(gating->msrnum);
 		msr.hi |= gating->msr.hi;
 		msr.lo |= gating->msr.lo;
-		/* printk_debug("%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__,
+		/* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__,
 		   gating->msrnum, msr.hi, msr.lo); */// GX3
 		wrmsr(gating->msrnum, msr);	// MSR - See the table above
 		gating += 1;
@@ -454,7 +454,7 @@
 		msr.hi |= prio->msr.hi;
 		msr.lo &= ~0xfff;
 		msr.lo |= prio->msr.lo;
-		/* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__,
+		/* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__,
 		   prio->msrnum, msr.hi, msr.lo);  */// GX3
 		wrmsr(prio->msrnum, msr);	// MSR - See the table above
 		prio += 1;
@@ -651,7 +651,7 @@
 
 	// now program RCONF_DEFAULT
 	wrmsr(CPU_RCONF_DEFAULT, msr);
-	printk_debug("CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi,
+	printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi,
 		     msr.lo);
 
 	// RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties.
@@ -663,7 +663,7 @@
 	    (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
 	wrmsr(CPU_RCONF_BYPASS, msr);
 
-	printk_debug("CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi,
+	printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi,
 		     msr.lo);
 }
 
@@ -695,7 +695,7 @@
 	msr.lo = 0x0f;
 	wrmsr(CPU_BC_L2_CONF, msr);
 
-	printk_debug("L2 cache enabled\n");
+	printk(BIOS_DEBUG, "L2 cache enabled\n");
 }
 
 static void setup_lx_cache(void)
@@ -748,7 +748,7 @@
 void northbridge_init_early(void)
 {
 	int i;
-	printk_debug("Enter %s\n", __func__);
+	printk(BIOS_DEBUG, "Enter %s\n", __func__);
 
 	for (i = 0; gliutables[i]; i++)
 		GLIUInit(gliutables[i]);
@@ -768,5 +768,5 @@
 	ClockGatingInit();
 
 	__asm__ __volatile__("FINIT\n");
-	printk_debug("Exit %s\n", __func__);
+	printk(BIOS_DEBUG, "Exit %s\n", __func__);
 }
diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c
index 75ed33e..cc82e2f 100644
--- a/src/northbridge/intel/e7501/debug.c
+++ b/src/northbridge/intel/e7501/debug.c
@@ -40,7 +40,7 @@
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
 #if CONFIG_USE_INIT
-                        printk_debug("\r\n%02x:",i);
+                        printk(BIOS_DEBUG, "\r\n%02x:",i);
 #else
 			print_debug("\r\n");
 			print_debug_hex8(i);
@@ -49,7 +49,7 @@
 		}
 		val = pci_read_config8(dev, i);
 #if CONFIG_USE_INIT
-		printk_debug(" %02x", val);
+		printk(BIOS_DEBUG, " %02x", val);
 #else
 		print_debug_char(' ');
 		print_debug_hex8(val);
@@ -102,7 +102,7 @@
 		if (device) {
 			int j;
 #if CONFIG_USE_INIT
-			printk_debug("dimm: %02x.0: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
 #else
 			print_debug("dimm: "); 
 			print_debug_hex8(i); 
@@ -114,7 +114,7 @@
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
 #if CONFIG_USE_INIT
-					printk_debug("\r\n%02x: ", j);
+					printk(BIOS_DEBUG, "\r\n%02x: ", j);
 #else
 					print_debug("\r\n");
 					print_debug_hex8(j);
@@ -127,7 +127,7 @@
 				}
 				byte = status & 0xff;
 #if CONFIG_USE_INIT
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 #else
 				print_debug_hex8(byte);
 				print_debug_char(' ');
@@ -139,7 +139,7 @@
 		if (device) {
 			int j;
 #if CONFIG_USE_INIT
-                        printk_debug("dimm: %02x.1: %02x", i, device);
+                        printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
 #else`
 			print_debug("dimm: "); 
 			print_debug_hex8(i); 
@@ -151,7 +151,7 @@
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
 #if CONFIG_USE_INIT
-                                        printk_debug("\r\n%02x: ", j);
+                                        printk(BIOS_DEBUG, "\r\n%02x: ", j);
 #else
 					print_debug("\r\n");
 					print_debug_hex8(j);
@@ -164,7 +164,7 @@
 				}
 				byte = status & 0xff;
 #if CONFIG_USE_INIT
-                                printk_debug("%02x ", byte);
+                                printk(BIOS_DEBUG, "%02x ", byte);
 #else
 				print_debug_hex8(byte);
 				print_debug_char(' ');
@@ -182,7 +182,7 @@
                 int j;
 		if( smbus_read_byte(device, 0) < 0 ) continue;
 #if CONFIG_USE_INIT
-		printk_debug("smbus: %02x", device);
+		printk(BIOS_DEBUG, "smbus: %02x", device);
 #else
                 print_debug("smbus: ");
                 print_debug_hex8(device);
@@ -196,7 +196,7 @@
                         }
                         if ((j & 0xf) == 0) {
 #if CONFIG_USE_INIT
-				printk_debug("\r\n%02x: ",j);
+				printk(BIOS_DEBUG, "\r\n%02x: ",j);
 #else
                 	        print_debug("\r\n");
                                 print_debug_hex8(j);
@@ -205,7 +205,7 @@
                         }
                         byte = status & 0xff;
 #if CONFIG_USE_INIT
-                        printk_debug("%02x ", byte);
+                        printk(BIOS_DEBUG, "%02x ", byte);
 #else
                         print_debug_hex8(byte);
                         print_debug_char(' ');
@@ -220,7 +220,7 @@
 
 	int i;
 #if CONFIG_USE_INIT
-	printk_debug("%04x:\r\n", port);
+	printk(BIOS_DEBUG, "%04x:\r\n", port);
 #else
         print_debug_hex16(port);
         print_debug(":\r\n");
@@ -229,7 +229,7 @@
                 uint8_t val;
                 if ((i & 0x0f) == 0) {
 #if CONFIG_USE_INIT
-			printk_debug("%02x:", i);
+			printk(BIOS_DEBUG, "%02x:", i);
 #else
                         print_debug_hex8(i);
                         print_debug_char(':');
@@ -237,7 +237,7 @@
                 }
                 val = inb(port);
 #if CONFIG_USE_INIT
-		printk_debug(" %02x",val);
+		printk(BIOS_DEBUG, " %02x",val);
 #else
                 print_debug_char(' ');
                 print_debug_hex8(val);
@@ -256,7 +256,7 @@
         for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
 #if CONFIG_USE_INIT
-			printk_debug("\r\n%08x:", i);
+			printk(BIOS_DEBUG, "\r\n%08x:", i);
 #else	
 			print_debug("\r\n");
 			print_debug_hex32(i);
@@ -264,7 +264,7 @@
 #endif
 		}
 #if CONFIG_USE_INIT	
-		printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
 #else
 		print_debug(" ");
              	print_debug_hex8((unsigned char)*((unsigned char *)i));
diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c
index fd9b094..efb7f02 100644
--- a/src/northbridge/intel/e7520/northbridge.c
+++ b/src/northbridge/intel/e7520/northbridge.c
@@ -65,7 +65,7 @@
         pci_tolm = find_pci_tolm(&dev->link[0]);
 
 #if 1
-	printk_debug("PCI mem marker = %x\n", pci_tolm);
+	printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
 #endif
 	/* FIXME Me temporary hack */
 	if(pci_tolm > 0xe0000000)
diff --git a/src/northbridge/intel/e7520/pciexp_porta.c b/src/northbridge/intel/e7520/pciexp_porta.c
index 70e5807..07440e3 100644
--- a/src/northbridge/intel/e7520/pciexp_porta.c
+++ b/src/northbridge/intel/e7520/pciexp_porta.c
@@ -30,12 +30,12 @@
 	int flag = 0;
 	do {
 		val = pci_read_config16(dev, 0x76);
-		printk_debug("pcie porta 0x76: %02x\n", val);
+		printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);
 		if((val & (1<<10) )&&(!flag)) { /* training error */
 			ctl = pci_read_config16(dev, 0x74);
 			pci_write_config16(dev, 0x74, (ctl | (1<<5)));
 			val = pci_read_config16(dev, 0x76);
-			printk_debug("pcie porta reset 0x76: %02x\n", val);
+			printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);
 			flag=1;
 			hard_reset();
 		}
diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c
index 3c483a1..02bf119 100644
--- a/src/northbridge/intel/e7525/northbridge.c
+++ b/src/northbridge/intel/e7525/northbridge.c
@@ -65,7 +65,7 @@
         pci_tolm = find_pci_tolm(&dev->link[0]);
 
 #if 1
-	printk_debug("PCI mem marker = %x\n", pci_tolm);
+	printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
 #endif
 	/* FIXME Me temporary hack */
 	if(pci_tolm > 0xe0000000)
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index 0a04faf..195790f 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -86,7 +86,7 @@
         pci_tolm = find_pci_tolm(&dev->link[0]);
 
 #if 1
-	printk_debug("PCI mem marker = %x\n", pci_tolm);
+	printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
 #endif
 	/* FIXME Me temporary hack */
 	if(pci_tolm > 0xe0000000)
diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c
index b94094e..df375ee 100644
--- a/src/northbridge/intel/i3100/pciexp_porta.c
+++ b/src/northbridge/intel/i3100/pciexp_porta.c
@@ -52,12 +52,12 @@
 	int flag = 0;
 	do {
 		val = pci_read_config16(dev, 0x76);
-		printk_debug("pcie porta 0x76: %02x\n", val);
+		printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);
 		if ((val & (1<<10)) && (!flag)) { /* training error */
 			ctl = pci_read_config16(dev, 0x74);
 			pci_write_config16(dev, 0x74, (ctl | (1<<5)));
 			val = pci_read_config16(dev, 0x76);
-			printk_debug("pcie porta reset 0x76: %02x\n", val);
+			printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);
 			flag=1;
 			hard_reset();
 		}
diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
index d51227c..aff287c 100644
--- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
+++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
@@ -44,7 +44,7 @@
 		pci_write_config32(dev, 0x3c, config->intrline);
 	}
 
-	printk_spew("configure PCIe port as \"Slot Implemented\"\n");
+	printk(BIOS_SPEW, "configure PCIe port as \"Slot Implemented\"\n");
 	val = pci_read_config16(dev, 0x66);
 	val &= ~(1<<8);
 	val |= 1<<8;
@@ -58,7 +58,7 @@
 {
 	u8 val8;
 	if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-		printk_spew("Enable VGA IO/MEM forwarding on PCIe port\n");
+		printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n");
 		pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8);
 		
 		dev->command |= PCI_COMMAND_IO;
@@ -76,12 +76,12 @@
 	int flag = 0;
 	do {
 		val = pci_read_config16(dev, 0x76);
-		printk_debug("pcie porta 0x76: %02x\n", val);
+		printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);
 		if ((val & (1<<11)) && (!flag)) { /* training error */
 			ctl = pci_read_config16(dev, 0x74);
 			pci_write_config16(dev, 0x74, (ctl | (1<<5)));
 			val = pci_read_config16(dev, 0x76);
-			printk_debug("pcie porta reset 0x76: %02x\n", val);
+			printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);
 			flag=1;
 			hard_reset();
 		}
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index 35ab611..fab224d 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -39,25 +39,25 @@
 {
 	unsigned device;
 	device = SMBUS_MEM_DEVICE_START;
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 	while(device <= SMBUS_MEM_DEVICE_END) {
 		int status = 0;
 		int i;
-		printk_debug("dimm %02x", device);
+		printk(BIOS_DEBUG, "dimm %02x", device);
 		for(i = 0; (i < 256) && (status == 0); i++) {
 			unsigned char byte;
 			if ((i % 20) == 0) {
-				printk_debug("\n%3d: ", i);
+				printk(BIOS_DEBUG, "\n%3d: ", i);
 			}
 			status = smbus_read_byte(device, i, &byte);
 			if (status != 0) {
-				printk_debug("bad device\n");
+				printk(BIOS_DEBUG, "bad device\n");
 				continue;
 			}
-			printk_debug("%02x ", byte);
+			printk(BIOS_DEBUG, "%02x ", byte);
 		}
 		device += SMBUS_MEM_DEVICE_INC;
-		printk_debug("\n");
+		printk(BIOS_DEBUG, "\n");
 	}
 }
 #endif
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index 4431aafa..772ab1c 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -15,7 +15,7 @@
 
 static void northbridge_init(device_t dev)
 {
-	printk_spew("Northbridge Init\n");
+	printk(BIOS_SPEW, "Northbridge Init\n");
 }
 
 static struct device_operations northbridge_operations = {
@@ -97,7 +97,7 @@
 		/* Convert to KB. */
 		tomk *= (8 * 1024);
 
-		printk_debug("Setting RAM size to %ld MB\n", tomk / 1024);
+		printk(BIOS_DEBUG, "Setting RAM size to %ld MB\n", tomk / 1024);
 
 		/* Compute the top of low memory. */
 		tolmk = pci_tolm / 1024;
diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c
index 41cc43b..ebe38af 100644
--- a/src/northbridge/intel/i440lx/northbridge.c
+++ b/src/northbridge/intel/i440lx/northbridge.c
@@ -43,7 +43,7 @@
  */
 static void northbridge_init(device_t dev)
 {
-	printk_spew("Northbridge Init\n");
+	printk(BIOS_SPEW, "Northbridge Init\n");
 }
 
 static struct device_operations northbridge_operations = {
@@ -125,7 +125,7 @@
 		/* Convert to KB. */
 		tomk *= (8 * 1024);
 
-		printk_debug("Setting RAM size to %lu MB\n", tomk / 1024);
+		printk(BIOS_DEBUG, "Setting RAM size to %lu MB\n", tomk / 1024);
 
 		/* Compute the top of low memory. */
 		tolmk = pci_tolm / 1024;
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c
index 4c171ef..5d07441 100644
--- a/src/northbridge/intel/i440lx/raminit.c
+++ b/src/northbridge/intel/i440lx/raminit.c
@@ -244,7 +244,7 @@
 #if 0
 	uint16_t reg16;
 	reg16 = pci_read_config16(NB, PACCFG); 
-	printk_debug("i82443LX Host Freq: 6%C MHz\r\n", (reg16 & 0x4000) ? '0' : '6');
+	printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\r\n", (reg16 & 0x4000) ? '0' : '6');
 #endif
 
 	PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c
index 2129c1b..23e7acf 100644
--- a/src/northbridge/intel/i82810/northbridge.c
+++ b/src/northbridge/intel/i82810/northbridge.c
@@ -34,7 +34,7 @@
 
 static void northbridge_init(device_t dev)
 {
-	printk_spew("Northbridge init\n");
+	printk(BIOS_SPEW, "Northbridge init\n");
 }
 
 static struct device_operations northbridge_operations = {
@@ -142,7 +142,7 @@
 		drp_value = drp_value >> 4;	// >>= 4; //? mess with later
 		tomk += (unsigned long)(translate_i82810_to_mb[drp_value]);
 
-		printk_debug("Setting RAM size to %d MB\n", tomk);
+		printk(BIOS_DEBUG, "Setting RAM size to %d MB\n", tomk);
 
 		/* Convert tomk from MB to KB. */
 		tomk = tomk << 10;
@@ -151,12 +151,12 @@
 		/* Check for VGA reserved memory. */
 		if (CONFIG_VIDEO_MB == 512) {
 			tomk -= 512;
-			printk_debug("Allocating %s RAM for VGA\n", "512KB");
+			printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "512KB");
 		} else if (CONFIG_VIDEO_MB == 1) {
 			tomk -= 1024 ;
-			printk_debug("Allocating %s RAM for VGA\n", "1MB");
+			printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "1MB");
 		} else {
-			printk_debug("Allocating %s RAM for VGA\n", "0MB");
+			printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "0MB");
 		}
 #endif
 
diff --git a/src/northbridge/intel/i82830/i82830_smihandler.c b/src/northbridge/intel/i82830/i82830_smihandler.c
index 1c45927..e53d283 100644
--- a/src/northbridge/intel/i82830/i82830_smihandler.c
+++ b/src/northbridge/intel/i82830/i82830_smihandler.c
@@ -80,17 +80,17 @@
 static void
 dump(u8 * addr, u32 len)
 {
-	printk_debug("\n%s(%p, %x):\n", __func__, addr, len);
+	printk(BIOS_DEBUG, "\n%s(%p, %x):\n", __func__, addr, len);
 	while (len) {
 		unsigned int tmpCnt = len;
 		unsigned char x;
 		if (tmpCnt > 8)
 			tmpCnt = 8;
-		printk_debug("\n%p: ", addr);
+		printk(BIOS_DEBUG, "\n%p: ", addr);
 		// print hex
 		while (tmpCnt--) {
 			x = *addr++;
-			printk_debug("%02x ", x);
+			printk(BIOS_DEBUG, "%02x ", x);
 		}
 		tmpCnt = len;
 		if (tmpCnt > 8)
@@ -105,10 +105,10 @@
 				//non-printable char
 				x = '.';
 			}
-			printk_debug("%c", x);
+			printk(BIOS_DEBUG, "%c", x);
 		}
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 #endif
 
@@ -150,19 +150,19 @@
 static void mbi_call(u8 subf, banner_id_t *banner_id)
 {
 #ifdef DEBUG_SMI_I82830
-	printk_debug("MBI\n");
-	printk_debug("|- sub function %x\n", subf);
-	printk_debug("|- banner id @ %x\n", (u32)banner_id);
-	printk_debug("|  |- mhid %x\n", banner_id->mhid);
-	printk_debug("|  |- function %x\n", banner_id->function);
-	printk_debug("|  |- return status %x\n", banner_id->retsts);
-	printk_debug("|  |- rfu %x\n", banner_id->rfu);
+	printk(BIOS_DEBUG, "MBI\n");
+	printk(BIOS_DEBUG, "|- sub function %x\n", subf);
+	printk(BIOS_DEBUG, "|- banner id @ %x\n", (u32)banner_id);
+	printk(BIOS_DEBUG, "|  |- mhid %x\n", banner_id->mhid);
+	printk(BIOS_DEBUG, "|  |- function %x\n", banner_id->function);
+	printk(BIOS_DEBUG, "|  |- return status %x\n", banner_id->retsts);
+	printk(BIOS_DEBUG, "|  |- rfu %x\n", banner_id->rfu);
 #endif
 
 	switch(banner_id->function) {
 	case 0x0001: {
 		version_t *version;
-		printk_debug("|- MBI_QueryInterface\n");
+		printk(BIOS_DEBUG, "|- MBI_QueryInterface\n");
 		version = (version_t *)banner_id;
 		version->banner.retsts = MSH_OK;
 		version->versionmajor=1;
@@ -171,18 +171,18 @@
 		break;
 	}
 	case 0x0002:
-		printk_debug("|- MBI_Attach\n");
-		printk_debug("|  |- Not Implemented!\n");
+		printk(BIOS_DEBUG, "|- MBI_Attach\n");
+		printk(BIOS_DEBUG, "|  |- Not Implemented!\n");
 		break;
 	case 0x0003:
-		printk_debug("|- MBI_Detach\n");
-		printk_debug("|  |- Not Implemented!\n");
+		printk(BIOS_DEBUG, "|- MBI_Detach\n");
+		printk(BIOS_DEBUG, "|  |- Not Implemented!\n");
 		break;
 	case 0x0201: {
 		obj_header_t *obj_header = (obj_header_t *)banner_id;
 		mbi_header_t *mbi_header = NULL;
-		printk_debug("|- MBI_GetObjectHeader\n");
-		printk_debug("|  |- objnum = %d\n", obj_header->objnum);
+		printk(BIOS_DEBUG, "|- MBI_GetObjectHeader\n");
+		printk(BIOS_DEBUG, "|  |- objnum = %d\n", obj_header->objnum);
 
 		int i, count=0;
 		obj_header->banner.retsts = MSH_IF_NOT_FOUND;
@@ -201,15 +201,15 @@
 			if (obj_header->objnum == count) {
 				int headerlen = ALIGN(sizeof(mbi_header) + mbi_header->name_len + 15, 16);
 #ifdef DEBUG_SMI_I82830
-				printk_debug("|  |- headerlen = %d\n", headerlen);
+				printk(BIOS_DEBUG, "|  |- headerlen = %d\n", headerlen);
 #endif
 				memcpy(&obj_header->header, mbi_header, headerlen);
 				obj_header->banner.retsts = MSH_OK;
-				printk_debug("|     |- MBI module '");
+				printk(BIOS_DEBUG, "|     |- MBI module '");
 				int j;
 				for (j=0; j < mbi_header->name_len && mbi_header->name[j]; j++)
-					printk_debug("%c",  mbi_header->name[j]);
-				printk_debug("' found.\n");
+					printk(BIOS_DEBUG, "%c",  mbi_header->name[j]);
+				printk(BIOS_DEBUG, "' found.\n");
 #ifdef DEBUG_SMI_I82830
 				dump(banner_id, sizeof(obj_header_t) + 16);
 #endif
@@ -219,21 +219,21 @@
 			count++;
 		}
 		if (obj_header->banner.retsts == MSH_IF_NOT_FOUND) 
-			printk_debug("|     |- MBI object #%d not found.\n", obj_header->objnum);
+			printk(BIOS_DEBUG, "|     |- MBI object #%d not found.\n", obj_header->objnum);
 		break;
 	}
 	case 0x0203: {
 		get_object_t *getobj = (get_object_t *)banner_id;
 		mbi_header_t *mbi_header = NULL;
-		printk_debug("|- MBI_GetObject\n");
+		printk(BIOS_DEBUG, "|- MBI_GetObject\n");
 #ifdef DEBUG_SMI_I82830
-		printk_debug("|  |- handle = %016lx\n", getobj->handle);
+		printk(BIOS_DEBUG, "|  |- handle = %016lx\n", getobj->handle);
 #endif
-		printk_debug("|  |- objnum = %d\n", getobj->objnum);
-		printk_debug("|  |- start = %x\n", getobj->start);
-		printk_debug("|  |- numbytes = %x\n", getobj->numbytes);
-		printk_debug("|  |- buflen = %x\n", getobj->buflen);
-		printk_debug("|  |- buffer = %x\n", getobj->buffer);
+		printk(BIOS_DEBUG, "|  |- objnum = %d\n", getobj->objnum);
+		printk(BIOS_DEBUG, "|  |- start = %x\n", getobj->start);
+		printk(BIOS_DEBUG, "|  |- numbytes = %x\n", getobj->numbytes);
+		printk(BIOS_DEBUG, "|  |- buflen = %x\n", getobj->buflen);
+		printk(BIOS_DEBUG, "|  |- buffer = %x\n", getobj->buffer);
 
 		int i, count=0;
 		getobj->banner.retsts = MSH_IF_NOT_FOUND;
@@ -250,7 +250,7 @@
 			len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + mbi_header->name_len, 16);
 			
 			if (getobj->objnum == count) {
-				printk_debug("|  |- len = %x\n", len);
+				printk(BIOS_DEBUG, "|  |- len = %x\n", len);
 				memcpy((void *)(getobj->buffer + OBJ_OFFSET),
 						((char *)mbi_header) + 0x20 , (len > getobj->buflen ? getobj->buflen : len));
 
@@ -264,15 +264,15 @@
 			count++;
 		}
 		if (getobj->banner.retsts == MSH_IF_NOT_FOUND) 
-			printk_debug("MBI module %d not found.\n", getobj->objnum);
+			printk(BIOS_DEBUG, "MBI module %d not found.\n", getobj->objnum);
 		break;
 	}
 	default:
-		printk_debug("|- function %x\n", banner_id->function);
-		printk_debug("|  |- Unknown Function!\n");
+		printk(BIOS_DEBUG, "|- function %x\n", banner_id->function);
+		printk(BIOS_DEBUG, "|  |- Unknown Function!\n");
 		break;
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 	//dump(banner_id, 0x20);
 }
 
@@ -291,7 +291,7 @@
 {
 	u32 mmio = pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
 	// mmio &= 0xfff80000;
-	// printk_debug("mmio=%x\n", mmio);
+	// printk(BIOS_DEBUG, "mmio=%x\n", mmio);
 	u16 swsmi = pci_read_config16(PCI_DEV(0, 0x02, 0), 0xe0);
 
 	if (!(swsmi & 1))
@@ -301,7 +301,7 @@
 
 	switch ((swsmi>>1) & 0xf) {
 	case 0:
-		printk_debug("Interface Function Presence Test.\n");
+		printk(BIOS_DEBUG, "Interface Function Presence Test.\n");
 		swsmi = 0;
 		swsmi &= ~(7 << 5); // Exit: Result
 		swsmi |= (SMI_IFC_SUCCESS << 5);
@@ -312,11 +312,11 @@
 		write32(mmio + 0x71428, 0x494e5443);
 		return;
 	case 4:
-		printk_debug("Get BIOS Data.\n");
-		printk_debug("swsmi=%04x\n", swsmi);
+		printk(BIOS_DEBUG, "Get BIOS Data.\n");
+		printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
 		break;
 	case 5:
-		printk_debug("Call MBI Functions.\n");
+		printk(BIOS_DEBUG, "Call MBI Functions.\n");
 		mbi_call(swsmi >> 8, (banner_id_t *)((read32(mmio + 0x71428) & 0x000fffff) + OBJ_OFFSET) );
 		// swsmi = 0x0000;
 		swsmi &= ~(7 << 5); // Exit: Result
@@ -324,11 +324,11 @@
 		pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
 		return;
 	case 6:
-		printk_debug("System BIOS Callbacks.\n");
-		printk_debug("swsmi=%04x\n", swsmi);
+		printk(BIOS_DEBUG, "System BIOS Callbacks.\n");
+		printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
 		break;
 	default:
-		printk_debug("Unknown SMI interface call %04x\n", swsmi);
+		printk(BIOS_DEBUG, "Unknown SMI interface call %04x\n", swsmi);
 		break;
 	}
 
@@ -354,15 +354,15 @@
 
 static void dump_err_status(u32 errsts)
 {
-	printk_debug("ERRSTS: ");
-	if (errsts & (1 << 12)) printk_debug("MBI ");
-	if (errsts & (1 <<  9)) printk_debug("LCKF ");
-	if (errsts & (1 <<  8)) printk_debug("DTF ");
-	if (errsts & (1 <<  5)) printk_debug("UNSC ");
-	if (errsts & (1 <<  4)) printk_debug("OOGF ");
-	if (errsts & (1 <<  3)) printk_debug("IAAF ");
-	if (errsts & (1 <<  2)) printk_debug("ITTEF ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "ERRSTS: ");
+	if (errsts & (1 << 12)) printk(BIOS_DEBUG, "MBI ");
+	if (errsts & (1 <<  9)) printk(BIOS_DEBUG, "LCKF ");
+	if (errsts & (1 <<  8)) printk(BIOS_DEBUG, "DTF ");
+	if (errsts & (1 <<  5)) printk(BIOS_DEBUG, "UNSC ");
+	if (errsts & (1 <<  4)) printk(BIOS_DEBUG, "OOGF ");
+	if (errsts & (1 <<  3)) printk(BIOS_DEBUG, "IAAF ");
+	if (errsts & (1 <<  2)) printk(BIOS_DEBUG, "ITTEF ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c
index da76a5d..5cd13b7 100644
--- a/src/northbridge/intel/i82830/northbridge.c
+++ b/src/northbridge/intel/i82830/northbridge.c
@@ -35,7 +35,7 @@
 
 static void northbridge_init(device_t dev)
 {
-	printk_spew("Northbridge init\n");
+	printk(BIOS_SPEW, "Northbridge init\n");
 }
 
 static struct device_operations northbridge_operations = {
@@ -95,7 +95,7 @@
 
 int add_northbridge_resources(struct lb_memory *mem)
 {
-	printk_debug("Adding IGD UMA memory area\n");
+	printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
 
@@ -120,10 +120,10 @@
 
 		if (CONFIG_VIDEO_MB == 512) {
 			igd_memory = (CONFIG_VIDEO_MB);
-			printk_debug("%dKB IGD UMA\n", igd_memory >> 10);
+			printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10);
 		} else {
 			igd_memory = (CONFIG_VIDEO_MB * 1024);
-			printk_debug("%dMB IGD UMA\n", igd_memory >> 10);
+			printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10);
 		}
 
 		/* Get the value of the highest DRB. This tells the end of
@@ -136,7 +136,7 @@
 		/* For reserving UMA memory in the memory map */
 		uma_memory_base = tomk * 1024ULL;
 		uma_memory_size = igd_memory * 1024ULL;
-		printk_debug("Available memory: %ldKB\n", tomk);
+		printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk);
 
 		/* Compute the top of low memory. */
 		tolmk = pci_tolm >> 10;
diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c
index ccab697..37c9674 100644
--- a/src/northbridge/intel/i82830/vga.c
+++ b/src/northbridge/intel/i82830/vga.c
@@ -31,21 +31,21 @@
 
 static void vga_init(device_t dev)
 {
-	printk_info("Starting Graphics Initialization\n");
+	printk(BIOS_INFO, "Starting Graphics Initialization\n");
 	struct cbfs_file *file = cbfs_find("mbi.bin");
 	void *mbi = NULL;
 	unsigned int mbi_len = 0;
 
 	if (file) {
 		if (ntohl(file->type) != CBFS_TYPE_MBI) {
-			printk_info( "CBFS:  MBI binary is of type %x instead of"
+			printk(BIOS_INFO,  "CBFS:  MBI binary is of type %x instead of"
 			       "type %x\n", file->type, CBFS_TYPE_MBI);
 		} else {
 			mbi = (void *) CBFS_SUBHEADER(file);
 			mbi_len = file->len;
 		}
 	} else {
-		printk_info( "Could not find MBI.\n");
+		printk(BIOS_INFO,  "Could not find MBI.\n");
 	}
 
 	if (mbi && mbi_len) {
@@ -59,7 +59,7 @@
 	}
 
 	pci_dev_init(dev);
-	printk_info("Graphics Initialization Complete\n");
+	printk(BIOS_INFO, "Graphics Initialization Complete\n");
 
 	/* Enable TV-Out */
 #if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
@@ -68,7 +68,7 @@
 #define PIPE_A_TV	(1 << 3)
 #define PIPE_B_CRT	(1 << 8)
 #define PIPE_B_TV	(1 << 10)
-	printk_debug("Enabling TV-Out\n"); 
+	printk(BIOS_DEBUG, "Enabling TV-Out\n"); 
 	void runInt10(void);
 	M.x86.R_AX = 0x5f64;
 	M.x86.R_BX = 0x0001; // Set Display Device, force execution
@@ -77,13 +77,13 @@
 	runInt10();
 	switch (M.x86.R_AX) {
 	case 0x005f:
-		printk_debug("... failed.\n");
+		printk(BIOS_DEBUG, "... failed.\n");
 		break;
 	case 0x015f:
-		printk_debug("... ok.\n");
+		printk(BIOS_DEBUG, "... ok.\n");
 		break;
 	default:
-		printk_debug("... not supported.\n");
+		printk(BIOS_DEBUG, "... not supported.\n");
 		break;
 	}
 #endif
diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c
index e33338e..8587754 100644
--- a/src/northbridge/intel/i855/northbridge.c
+++ b/src/northbridge/intel/i855/northbridge.c
@@ -79,13 +79,13 @@
 	device_t mc_dev;
         uint32_t pci_tolm;
         
-        printk_debug("Entered with dev vid = %x\n", dev->vendor);
-	printk_debug("Entered with dev did = %x\n", dev->device);
+        printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor);
+	printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device);
 
         pci_tolm = find_pci_tolm(&dev->link[0]);	
 	mc_dev = dev->link[0].children->sibling;
-	printk_debug("MC dev vendor = %x\n", mc_dev->vendor);
-	printk_debug("MC dev device = %x\n", mc_dev->device);
+	printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor);
+	printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device);
 	
 	if (mc_dev) {
 		/* Figure out which areas are/should be occupied by RAM.
@@ -120,8 +120,8 @@
 		 */
 		 
 		/* Report the memory regions */
-		printk_debug("tomk = %d\n", tomk);
-		printk_debug("tolmk = %d\n", tolmk);
+		printk(BIOS_DEBUG, "tomk = %d\n", tomk);
+		printk(BIOS_DEBUG, "tolmk = %d\n", tolmk);
 
 		idx = 10;
 		/* avoid pam region */
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index 4a59fee..a14d0ce 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -36,9 +36,9 @@
 			(((id >> 16) & 0xffff) == 0x0000)) {
 			continue;
 		}
-		printk_debug("PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
+		printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
 			(dev >> 15) & 0x1f, (dev >> 12) & 7);
-		printk_debug(" [%04x:%04x]\n", id &0xffff, id >> 16);
+		printk(BIOS_DEBUG, " [%04x:%04x]\n", id &0xffff, id >> 16);
 	}
 }
 
@@ -46,17 +46,17 @@
 {
 	int i;
 
-	printk_debug("PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
+	printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
 
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("%02x:", i);
+			printk(BIOS_DEBUG, "%02x:", i);
 		}
 		val = pci_read_config8(dev, i);
-		printk_debug(" %02x", val);
+		printk(BIOS_DEBUG, " %02x", val);
 		if ((i & 0x0f) == 0x0f) {
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
 	}
 }
@@ -85,21 +85,21 @@
         while(device <= SMBUS_MEM_DEVICE_END) {
                 int status = 0;
                 int i;
-        	printk_debug("\ndimm %02x", device);
+        	printk(BIOS_DEBUG, "\ndimm %02x", device);
 		
                 for(i = 0; (i < 256) ; i++) {
                         if ((i % 16) == 0) {
-				printk_debug("\n%02x: ", i);
+				printk(BIOS_DEBUG, "\n%02x: ", i);
                         }
 			status = smbus_read_byte(device, i);
                         if (status < 0) {
-			         printk_debug("bad device: %02x\n", -status);
+			         printk(BIOS_DEBUG, "bad device: %02x\n", -status);
 			         break; 
 			}
-			printk_debug("%02x ", status);
+			printk(BIOS_DEBUG, "%02x ", status);
 		}
 		device += SMBUS_MEM_DEVICE_INC;
-		printk_debug("\n");
+		printk(BIOS_DEBUG, "\n");
 	}
 }
 
@@ -109,9 +109,9 @@
 	print_debug("dump_mem:");
         for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
         }
         print_debug("\n");
  }
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index d16f77a..f6cdcca 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -29,108 +29,108 @@
 {
 	u8 reg8;
 
-	printk_info("\n");
+	printk(BIOS_INFO, "\n");
 	reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4;
 	switch (reg8) {
 	case 1:
-		printk_info("Mobile Intel(R) 82945GM/GME Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express");
 		break;
 	case 2:
-		printk_info("Mobile Intel(R) 82945GMS/GU Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU Express");
 		break;
 	case 3:
-		printk_info("Mobile Intel(R) 82945PM Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express");
 		break;
 	case 5:
-		printk_info("Intel(R) 82945GT Express");
+		printk(BIOS_INFO, "Intel(R) 82945GT Express");
 		break;
 	case 6:
-		printk_info("Mobile Intel(R) 82943/82940GML Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express");
 		break;
 	default:
-		printk_info("Unknown (%02x)", reg8);	/* Others reserved. */
+		printk(BIOS_INFO, "Unknown (%02x)", reg8);	/* Others reserved. */
 	}
-	printk_info(" Chipset\n");
+	printk(BIOS_INFO, " Chipset\n");
 
-	printk_debug("(G)MCH capable of up to FSB ");
+	printk(BIOS_DEBUG, "(G)MCH capable of up to FSB ");
 	reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5;
 	switch (reg8) {
 	case 2:
-		printk_debug("800 MHz"); /* According to 965 spec */
+		printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */
 		break;
 	case 3:
-		printk_debug("667 MHz");
+		printk(BIOS_DEBUG, "667 MHz");
 		break;
 	case 4:
-		printk_debug("533 MHz");
+		printk(BIOS_DEBUG, "533 MHz");
 		break;
 	default:
-		printk_debug("N/A MHz (%02x)", reg8);
+		printk(BIOS_DEBUG, "N/A MHz (%02x)", reg8);
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 
-	printk_debug("(G)MCH capable of ");
+	printk(BIOS_DEBUG, "(G)MCH capable of ");
 	reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
 	switch (reg8) {
 	case 2:
-		printk_debug("up to DDR2-667");
+		printk(BIOS_DEBUG, "up to DDR2-667");
 		break;
 	case 3:
-		printk_debug("up to DDR2-533");
+		printk(BIOS_DEBUG, "up to DDR2-533");
 		break;
 	case 4:
-		printk_debug("DDR2-400");
+		printk(BIOS_DEBUG, "DDR2-400");
 		break;
 	default:
-		printk_info("unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
+		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 static void i945_detect_chipset(void)
 {
 	u8 reg8;
 
-	printk_info("\nIntel(R) ");
+	printk(BIOS_INFO, "\nIntel(R) ");
 
 	reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3);
 	switch (reg8) {
 	case 0:
 	case 1:
-		printk_info("82945G");
+		printk(BIOS_INFO, "82945G");
 		break;
 	case 2:
 	case 3:
-		printk_info("82945P");
+		printk(BIOS_INFO, "82945P");
 		break;
 	case 4:
-		printk_info("82945GC");
+		printk(BIOS_INFO, "82945GC");
 		break;
 	case 5:
-		printk_info("82945GZ");
+		printk(BIOS_INFO, "82945GZ");
 		break;
 	case 6:
 	case 7:
-		printk_info("82945PL");
+		printk(BIOS_INFO, "82945PL");
 		break;
 	default:
 		break;
 	}
-	printk_info(" Chipset\n");
+	printk(BIOS_INFO, " Chipset\n");
 
-	printk_debug("(G)MCH capable of ");
+	printk(BIOS_DEBUG, "(G)MCH capable of ");
 	reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
 	switch (reg8) {
 	case 0:
-		printk_debug("up to DDR2-667");
+		printk(BIOS_DEBUG, "up to DDR2-667");
 		break;
 	case 3:
-		printk_debug("up to DDR2-533");
+		printk(BIOS_DEBUG, "up to DDR2-533");
 		break;
 	default:
-		printk_info("unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
+		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 static void i945_setup_bars(void)
@@ -139,11 +139,10 @@
 
 	/* As of now, we don't have all the A0 workarounds implemented */
 	if (i945_silicon_revision() == 0)
-		printk_info
-		    ("Warning: i945 silicon revision A0 might not work correctly.\n");
+		printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n");
 
 	/* Setting up Southbridge. In the northbridge code. */
-	printk_debug("Setting up static southbridge registers...");
+	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
 
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
@@ -152,14 +151,14 @@
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10);	/* Enable GPIOs */
 	setup_ich7_gpios();
-	printk_debug(" done.\n");
+	printk(BIOS_DEBUG, " done.\n");
 
-	printk_debug("Disabling Watchdog reboot...");
+	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
 	RCBA32(GCS) = (RCBA32(0x3410)) | (1 << 5);	/* No reset */
 	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
-	printk_debug(" done.\n");
+	printk(BIOS_DEBUG, " done.\n");
 
-	printk_debug("Setting up static northbridge registers...");
+	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
 	/* Set up all hardcoded northbridge BARs */
 	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
 	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
@@ -182,16 +181,16 @@
 	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
 
 	pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
-	printk_debug(" done.\n");
+	printk(BIOS_DEBUG, " done.\n");
 
 	/* Wait for MCH BAR to come up */
-	printk_debug("Waiting for MCHBAR to come up...");
+	printk(BIOS_DEBUG, "Waiting for MCHBAR to come up...");
 	if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */
 		do {
 			reg8 = *(volatile u8 *)0xfed40000;
 		} while (!(reg8 & 0x80));
 	}
-	printk_debug("ok\n");
+	printk(BIOS_DEBUG, "ok\n");
 }
 
 static void i945_setup_egress_port(void)
@@ -199,7 +198,7 @@
 	u32 reg32;
 	u32 timeout;
 
-	printk_debug("Setting up Egress Port RCRB\n");
+	printk(BIOS_DEBUG, "Setting up Egress Port RCRB\n");
 
 	/* Egress Port Virtual Channel 0 Configuration */
 
@@ -267,26 +266,26 @@
 	EPBAR32(EPVC1RCTL) |= (1 << 16);
 	EPBAR32(EPVC1RCTL) |= (1 << 16);
 
-	printk_debug("Loading port arbitration table ...");
+	printk(BIOS_DEBUG, "Loading port arbitration table ...");
 	/* Loop until bit 0 becomes 0 */
 	timeout = 0x7fffff;
 	while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("ok\n");
+		printk(BIOS_DEBUG, "ok\n");
 
 	/* Now enable VC1 */
 	EPBAR32(EPVC1RCTL) |= (1 << 31);
 
-	printk_debug("Wait for VC1 negotiation ...");
+	printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
 	/* Wait for VC1 negotiation pending */
 	timeout = 0x7fff;
 	while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("ok\n");
+		printk(BIOS_DEBUG, "ok\n");
 
 }
 
@@ -348,7 +347,7 @@
 
 	int activate_aspm = 1;
 
-	printk_debug("Setting up DMI RCRB\n");
+	printk(BIOS_DEBUG, "Setting up DMI RCRB\n");
 
 	/* Virtual Channel 0 Configuration */
 	reg32 = DMIBAR32(DMIVC0RCTL0);
@@ -373,14 +372,14 @@
 	/* Now enable VC1 */
 	DMIBAR32(DMIVC1RCTL) |= (1 << 31);
 
-	printk_debug("Wait for VC1 negotiation ...");
+	printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
 	/* Wait for VC1 negotiation pending */
 	timeout = 0x7ffff;
 	while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("done..\n");
+		printk(BIOS_DEBUG, "done..\n");
 #if 1
 	/* Enable Active State Power Management (ASPM) L0 state */
 
@@ -425,10 +424,10 @@
 	DMIBAR32(0x204) = reg32;
 
 	if (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x54) & ((1 << 4) | (1 << 3))) {	/* DEVEN */
-		printk_debug("Internal graphics: enabled\n");
+		printk(BIOS_DEBUG, "Internal graphics: enabled\n");
 		DMIBAR32(0x200) |= (1 << 21);
 	} else {
-		printk_debug("Internal graphics: disabled\n");
+		printk(BIOS_DEBUG, "Internal graphics: disabled\n");
 		DMIBAR32(0x200) &= ~(1 << 21);
 	}
 
@@ -474,13 +473,13 @@
 	}
 
 	/* wait for bit toggle to 0 */
-	printk_debug("Waiting for DMI hardware...");
+	printk(BIOS_DEBUG, "Waiting for DMI hardware...");
 	timeout = 0x7fffff;
 	while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("ok\n");
+		printk(BIOS_DEBUG, "ok\n");
 
 	DMIBAR32(0x1c4) = 0xffffffff;
 	DMIBAR32(0x1d0) = 0xffffffff;
@@ -495,8 +494,7 @@
 
 	if (i945_silicon_revision() == 1 && ((MCHBAR8(0xe08) & (1 << 5)) == 1)) {
 		if ((MCHBAR32(0x214) & 0xf) != 0x3) {
-			printk_info
-			    ("DMI link requires A1 stepping workaround. Rebooting.\n");
+			printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n");
 			reg32 = DMIBAR32(0x224);
 			reg32 &= ~(7 << 0);
 			reg32 |= (3 << 0);
@@ -515,7 +513,7 @@
 
 	u8 reg8;
 
-	printk_debug("Enabling PCI Express x16 Link\n");
+	printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n");
 
 	reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
 	reg16 |= DEVEN_D1F0;
@@ -540,7 +538,7 @@
 	pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
 
 	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
-	printk_debug("SLOTSTS: %04x\n", reg16);
+	printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
 	if (!(reg16 & 0x48)) {
 		goto disable_pciexpress_x16_link;
 	}
@@ -576,18 +574,18 @@
 	pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32);
 
 	/* Wait for training to succeed */
-	printk_debug("PCIe link training ...");
+	printk(BIOS_DEBUG, "PCIe link training ...");
 	timeout = 0x7ffff;
 	while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3)  && --timeout) ;
 
 	reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
 	if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
-		printk_debug(" Detected PCIe device %04x:%04x\n",
+		printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n",
 				reg32 & 0xffff, reg32 >> 16);
 	} else {
-		printk_debug(" timeout!\n");
+		printk(BIOS_DEBUG, " timeout!\n");
 
-		printk_debug("Restrain PCIe port to x1\n");
+		printk(BIOS_DEBUG, "Restrain PCIe port to x1\n");
 
 		reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214);
 		reg32 &= ~(0xf << 1);
@@ -601,17 +599,17 @@
 		reg16 &= ~(1 << 6);
 		pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
 
-		printk_debug("PCIe link training ...");
+		printk(BIOS_DEBUG, "PCIe link training ...");
 		timeout = 0x7ffff;
 		while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3)  && --timeout) ;
 
 		reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
 		if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
-			printk_debug(" Detected PCIe x1 device %04x:%04x\n",
+			printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n",
 				reg32 & 0xffff, reg32 >> 16);
 		} else {
-			printk_debug(" timeout!\n");
-			printk_debug("Disabling PCIe x16 port completely.\n");
+			printk(BIOS_DEBUG, " timeout!\n");
+			printk(BIOS_DEBUG, "Disabling PCIe x16 port completely.\n");
 			goto disable_pciexpress_x16_link;
 		}
 	}
@@ -620,7 +618,7 @@
 	reg16 >>= 4;
 	reg16 &= 0x3f;
 	/* reg16 == 1 -> x1; reg16 == 16 -> x16 */
-	printk_debug("PCIe x%d link training succeeded.\n", reg16);
+	printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16);
 
 	reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x204);
 	reg32 &= 0xfffffc00; /* clear [9:0] */
@@ -633,9 +631,9 @@
 	}
 
 	reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
-	printk_debug("PCIe device class: %06x\n", reg32);
+	printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32);
 	if (reg32 == 0x030000) {
-		printk_debug("PCIe device is VGA. Disabling IGD.\n");
+		printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n");
 		reg16 = (1 << 1);
 		pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16);
 
@@ -758,7 +756,7 @@
 
 disable_pciexpress_x16_link:
 	/* For now we just disable the x16 link */
-	printk_debug("Disabling PCI Express x16 Link\n");
+	printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n");
 
 	MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
 
@@ -774,14 +772,14 @@
 	reg16 &= ~(1 << 6);
 	pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
 
-	printk_debug("Wait for link to enter detect state... ");
+	printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
 	timeout = 0x7fffff;
 	for (reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214);
 	     (reg32 & 0x000f0000) && --timeout;) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("ok\n");
+		printk(BIOS_DEBUG, "ok\n");
 
 	/* Finally: Disable the PCI config header */
 	reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
@@ -793,7 +791,7 @@
 {
 	u32 reg32;
 
-	printk_debug("Setting up Root Complex Topology\n");
+	printk(BIOS_DEBUG, "Setting up Root Complex Topology\n");
 	/* Egress Port Root Topology */
 
 	reg32 = EPBAR32(EPESD);
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 5f71e19..1f5a035 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -75,11 +75,11 @@
 {
 	u32 pcie_config_base, pcie_config_size;
 
-	printk_debug("Adding UMA memory area\n");
+	printk(BIOS_DEBUG, "Adding UMA memory area\n");
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
 
-	printk_debug("Adding PCIe config bar\n");
+	printk(BIOS_DEBUG, "Adding PCIe config bar\n");
 	get_pcie_bar(&pcie_config_base, &pcie_config_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		pcie_config_base, pcie_config_size);
@@ -140,13 +140,13 @@
 	 * this way?
 	 */
 	pci_tolm = find_pci_tolm(&dev->link[0]);
-	printk_debug("pci_tolm: 0x%x\n", pci_tolm);
+	printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);
 
-	printk_spew("Base of stolen memory: 0x%08x\n",
+	printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
 		    pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
 
 	tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c);
-	printk_spew("Top of Low Used DRAM: 0x%08x\n", tolud << 24);
+	printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24);
 
 	tomk = tolud << 14;
 
@@ -154,7 +154,7 @@
 	reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
 	if (reg8 & 1) {
 		int tseg_size = 0;
-		printk_debug("TSEG decoded, subtracting ");
+		printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
 		reg8 >>= 1;
 		reg8 &= 3;
 		switch (reg8) {
@@ -169,14 +169,14 @@
 			break;	/* TSEG = 8M */
 		}
 
-		printk_debug("%dM\n", tseg_size >> 10);
+		printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10);
 		tomk -= tseg_size;
 	}
 
 	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
 	if (!(reg16 & 2)) {
 		int uma_size = 0;
-		printk_debug("IGD decoded, subtracting ");
+		printk(BIOS_DEBUG, "IGD decoded, subtracting ");
 		reg16 >>= 4;
 		reg16 &= 7;
 		switch (reg16) {
@@ -188,7 +188,7 @@
 			break;
 		}
 
-		printk_debug("%dM UMA\n", uma_size >> 10);
+		printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
 		tomk -= uma_size;
 
 		/* For reserving UMA memory in the memory map */
@@ -199,8 +199,8 @@
 	/* The following needs to be 2 lines, otherwise the second
 	 * number is always 0
 	 */
-	printk_info("Available memory: %dK", (uint32_t)tomk);
-	printk_info(" (%dM)\n", (uint32_t)(tomk >> 10));
+	printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk);
+	printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk >> 10));
 
 	/* Report the memory regions */
 	ram_resource(dev, 3, 0, 640);
@@ -253,7 +253,7 @@
 	resource->flags =
 	    IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
 	    IORESOURCE_ASSIGNED;
-	printk_debug("Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
+	printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
 		     (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
 }
 
@@ -289,15 +289,15 @@
 {
 	switch (pci_read_config32(dev, SKPAD)) {
 	case 0xcafebabe:
-		printk_debug("Normal boot.\n");
+		printk(BIOS_DEBUG, "Normal boot.\n");
 		acpi_slp_type=0;
 		break;
 	case 0xcafed00d:
-		printk_debug("S3 Resume.\n");
+		printk(BIOS_DEBUG, "S3 Resume.\n");
 		acpi_slp_type=3;
 		break;
 	default:
-		printk_debug("Unknown boot method, assuming normal.\n");
+		printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
 		acpi_slp_type=0;
 		break;
 	}
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 3f73549..444a360 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -25,7 +25,7 @@
 
 /* Debugging macros. */
 #if CONFIG_DEBUG_RAM_SETUP
-#define PRINTK_DEBUG(x...)	printk_debug(x)
+#define PRINTK_DEBUG(x...)	printk(BIOS_DEBUG, x)
 #else
 #define PRINTK_DEBUG(x...)
 #endif
@@ -74,12 +74,12 @@
 static void sdram_dump_mchbar_registers(void)
 {
 	int i;
-	printk_debug("Dumping MCHBAR Registers\n");
+	printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
 
 	for (i=0; i<0xfff; i+=4) {
 		if (MCHBAR32(i) == 0)
 			continue;
-		printk_debug("0x%04x: 0x%08x\n", i, MCHBAR32(i));
+		printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
 	}
 }
 #endif
@@ -94,7 +94,7 @@
 	case 1: return 400;
 	case 2: return 533;
 	case 3: return 667;
-	default: printk_debug("memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
+	default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
 	}
 	return -1;
 }
@@ -106,7 +106,7 @@
 	case 0: return 400;
 	case 1: return 533;
 	case 3: return 667;
-	default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
+	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 	}
 	return -1;
 }
@@ -118,7 +118,7 @@
 	case 0: return 1066;
 	case 1: return 533;
 	case 2: return 800;
-	default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
+	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 	}
 	return -1;
 }
@@ -234,7 +234,7 @@
 
 	if (reg8 & ((1<<7)|(1<<2))) {
 		if (reg8 & (1<<2)) {
-			printk_debug("SLP S4# Assertion Width Violation.\n");
+			printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
 			/* Write back clears bit 2 */
 			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 			do_reset = 1;
@@ -242,7 +242,7 @@
 		}
 
 		if (reg8 & (1<<7)) {
-			printk_debug("DRAM initialization was interrupted.\n");
+			printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
 			reg8 &= ~(1<<7);
 			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 			do_reset = 1;
@@ -254,7 +254,7 @@
 		pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 
 		if (do_reset) {
-			printk_debug("Reset required.\n");
+			printk(BIOS_DEBUG, "Reset required.\n");
 			outb(0x00, 0xcf9);
 			outb(0x0e, 0xcf9);
 			for (;;) asm("hlt"); /* Wait for reset! */
@@ -300,10 +300,10 @@
 
 	if (sdram_capabilities_dual_channel()) {
 		sysinfo->dual_channel = 1;
-		printk_debug("This mainboard supports Dual Channel Operation.\n");
+		printk(BIOS_DEBUG, "This mainboard supports Dual Channel Operation.\n");
 	} else {
 		sysinfo->dual_channel = 0;
-		printk_debug("This mainboard supports only Single Channel Operation.\n");
+		printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n");
 	}
 
 	/**
@@ -339,10 +339,10 @@
 		if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
 			continue;
 
-		printk_debug("DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
+		printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
 
 		if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
-			printk_debug("N/A\n");
+			printk(BIOS_DEBUG, "N/A\n");
 			continue;
 		}
 
@@ -360,29 +360,29 @@
 		case 0x08:
 			switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 			case 1:
-				printk_debug("x8DDS\n");
+				printk(BIOS_DEBUG, "x8DDS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
 				break;
 			case 0:
-				printk_debug("x8DS\n");
+				printk(BIOS_DEBUG, "x8DS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
 				break;
 			default:
-				printk_debug ("Unsupported.\n");
+				printk(BIOS_DEBUG, "Unsupported.\n");
 			}
 			break;
 		case 0x10:
 			switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 			case 1:
-				printk_debug("x16DS\n");
+				printk(BIOS_DEBUG, "x16DS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
 				break;
 			case 0:
-				printk_debug("x16SS\n");
+				printk(BIOS_DEBUG, "x16SS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
 				break;
 			default:
-				printk_debug ("Unsupported.\n");
+				printk(BIOS_DEBUG, "Unsupported.\n");
 			}
 			break;
 		default:
@@ -397,7 +397,7 @@
 	}
 
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		printk_info("Channel 0 has no memory populated.\n");
+		printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
 	}
 }
 
@@ -556,7 +556,7 @@
 	}
 
 	if (sysinfo->memory_frequency && sysinfo->cas) {
-		printk_debug("Memory will be driven at %dMHz with CAS=%d clocks\n",
+		printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n",
 				sysinfo->memory_frequency, sysinfo->cas);
 	} else {
 		die("Could not find common memory frequency and CAS\n");
@@ -599,7 +599,7 @@
 		die("DDR-II Module does not support this frequency (tRAS error)\n");
 	}
 
-	printk_debug("tRAS = %d cycles\n", tRAS_cycles);
+	printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles);
 	sysinfo->tras = tRAS_cycles;
 }
 
@@ -640,7 +640,7 @@
 		die("DDR-II Module does not support this frequency (tRP error)\n");
 	}
 
-	printk_debug("tRP = %d cycles\n", tRP_cycles);
+	printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles);
 	sysinfo->trp = tRP_cycles;
 }
 
@@ -680,7 +680,7 @@
 		die("DDR-II Module does not support this frequency (tRCD error)\n");
 	}
 
-	printk_debug("tRCD = %d cycles\n", tRCD_cycles);
+	printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles);
 	sysinfo->trcd = tRCD_cycles;
 }
 
@@ -720,7 +720,7 @@
 		die("DDR-II Module does not support this frequency (tWR error)\n");
 	}
 
-	printk_debug("tWR = %d cycles\n", tWR_cycles);
+	printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles);
 	sysinfo->twr = tWR_cycles;
 }
 
@@ -756,7 +756,7 @@
 			/* Can this happen? Go back to 127.5ns just to be sure
 			 * we don't run out of the array. This may be wrong
 			 */
-			printk_debug("DIMM %d is 1Gb x16.. Please report.\n", i);
+			printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i);
 			reg8 = 3;
 		}
 
@@ -772,7 +772,7 @@
 	}
 
 	sysinfo->trfc = tRFC_cycles[index];
-	printk_debug("tRFC = %d cycles\n", tRFC_cycles[index]);
+	printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]);
 }
 
 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
@@ -804,7 +804,7 @@
 
 		die("DDR-II module has unsupported refresh value\n");
 	}
-	printk_debug("Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
+	printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
 }
 
 static void sdram_verify_burst_length(struct sys_info * sysinfo)
@@ -1137,18 +1137,18 @@
 
 	/* Dual Channel needs different tables. */
 	if (sdram_capabilities_dual_channel()) {
-		printk_debug("Programming Dual Channel RCOMP\n");
+		printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n");
 		strength_multiplier = dual_channel_strength_multiplier;
 		dual_channel = 1;
 		idx = 5 * sysinfo->dimm[0] +  sysinfo->dimm[2];
 	} else {
-		printk_debug("Programming Single Channel RCOMP\n");
+		printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n");
 		strength_multiplier = single_channel_strength_multiplier;
 		dual_channel = 0;
 		idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
 	}
 
-	printk_debug("Table Index: %d\n", idx);
+	printk(BIOS_DEBUG, "Table Index: %d\n", idx);
 
 	MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
 	MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
@@ -1197,7 +1197,7 @@
 	u32 chan0dll = 0, chan1dll = 0;
 	int i;
 
-	printk_debug ("Programming DLL Timings... \n");
+	printk(BIOS_DEBUG, "Programming DLL Timings... \n");
 
 	MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
 	MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
@@ -1249,7 +1249,7 @@
 	u8 reg8;
 	u32 reg32;
 
-	printk_debug ("Initializing System Memory IO... \n");
+	printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
 	/* Enable Data Half Clock Pushout */
 	reg8 = MCHBAR8(C0HCTC);
 	reg8 &= ~0x1f;
@@ -1291,7 +1291,7 @@
 {
 	u32 reg32;
 
-	printk_debug ("Enabling System Memory IO... \n");
+	printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
 
 	reg32 = MCHBAR32(RCVENMT);
 	reg32 &= ~(0x3f << 6);
@@ -1401,7 +1401,7 @@
 	/* Don't die here, I have not come across any of these to test what
 	 * actually happens.
 	 */
-	printk_err("Assymetric DIMMs are not supported by this chipset\n");
+	printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
 
 	sz.side2 -= (rows & 0x0f);		/* Subtract out rows on side 1 */
 	sz.side2 += ((rows >> 4) & 0x0f);	/* Add in rows on side 2 */
@@ -1445,7 +1445,7 @@
 
 		sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
 
-		printk_debug("DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
+		printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
 
 		if (!sz.side2)
 			continue;
@@ -1456,7 +1456,7 @@
 
 		sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
 
-		printk_debug("DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
+		printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
 	}
 }
 
@@ -1465,7 +1465,7 @@
 	int i;
 	int cum0, cum1, tolud, tom;
 
-	printk_debug ("Setting RAM size... \n");
+	printk(BIOS_DEBUG, "Setting RAM size... \n");
 
 	cum0 = 0;
 	for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
@@ -1507,9 +1507,9 @@
 
 	pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
 
-	printk_debug("C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
-	printk_debug("C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
-	printk_debug("TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
+	printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
+	printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
+	printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
 
 	pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
 
@@ -1521,7 +1521,7 @@
 	int i, value;
 	u16 dra0=0, dra1=0, dra = 0;
 
-	printk_debug ("Setting row attributes... \n");
+	printk(BIOS_DEBUG, "Setting row attributes... \n");
 	for(i=0; i < 2 * DIMM_SOCKETS; i++) {
 		u16 device;
 		u8 columnsrows;
@@ -1561,8 +1561,8 @@
 	MCHBAR16(C0DRA0) = dra0;
 	MCHBAR16(C1DRA0) = dra1;
 
-	printk_debug("C0DRA = 0x%04x\n", dra0);
-	printk_debug("C1DRA = 0x%04x\n", dra1);
+	printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0);
+	printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1);
 
 	return 0;
 }
@@ -1587,7 +1587,7 @@
 		if (sysinfo->banks[i] != 8)
 			continue;
 
-		printk_spew("DIMM%d has 8 banks.\n", i);
+		printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i);
 
 		if (i & 1)
 			MCHBAR16(off32) |= 0x50;
@@ -1852,7 +1852,7 @@
 {
 	u32 reg32;
 
-	printk_debug("Setting mode of operation for memory channels...");
+	printk(BIOS_DEBUG, "Setting mode of operation for memory channels...");
 
 	if (sdram_capabilities_interleave() &&
 		    ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
@@ -1870,21 +1870,21 @@
 
 	if(sysinfo->interleaved) {
 		/* Dual Channel Interleaved */
-		printk_debug("Dual Channel Interleaved.\n");
+		printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
 		reg32 |= (1 << 1);
 	} else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
 			sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
 		/* Channel 1 only */
-		printk_debug("Single Channel 1 only.\n");
+		printk(BIOS_DEBUG, "Single Channel 1 only.\n");
 		reg32 |= (1 << 2);
 	} else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
 			SYSINFO_DIMM_NOT_POPULATED) {
 		/* Dual Channel Assymetric */
-		printk_debug("Dual Channel Assymetric.\n");
+		printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
 		reg32 |= (1 << 0);
 	} else {
 		/* All bits 0 means Single Channel 0 operation */
-		printk_debug("Single Channel 0 only.\n");
+		printk(BIOS_DEBUG, "Single Channel 0 only.\n");
 	}
 
 	reg32 |= (1 << 10);
@@ -1934,14 +1934,14 @@
 #define VOLTAGE_1_05	0x00
 #define VOLTAGE_1_50	0x01
 
-	printk_debug ("Setting Graphics Frequency... \n");
+	printk(BIOS_DEBUG, "Setting Graphics Frequency... \n");
 
-	printk_debug("FSB: %d MHz ", sysinfo->fsb_frequency);
+	printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency);
 
 	voltage = VOLTAGE_1_05;
 	if (MCHBAR32(DFT_STRAP1) & (1 << 20))
 		voltage = VOLTAGE_1_50;
-	printk_debug("Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
+	printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
 
 	/* Gate graphics hardware for frequency change */
 	reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
@@ -1971,12 +1971,12 @@
 			freq = CRCLK_166MHz;
 	}
 
-	printk_debug("Render: ");
+	printk(BIOS_DEBUG, "Render: ");
 	switch (freq) {
-	case CRCLK_166MHz: printk_debug("166Mhz"); break;
-	case CRCLK_200MHz: printk_debug("200Mhz"); break;
-	case CRCLK_250MHz: printk_debug("250Mhz"); break;
-	case CRCLK_400MHz: printk_debug("400Mhz"); break;
+	case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
+	case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
+	case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
+	case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
 	}
 
 	if (i945_silicon_revision() == 0) {
@@ -2021,10 +2021,10 @@
 
 	if (voltage == VOLTAGE_1_05) {
 		reg8 |= CDCLK_200MHz;
-		printk_debug(" Display: 200MHz\n");
+		printk(BIOS_DEBUG, " Display: 200MHz\n");
 	} else {
 		reg8 |= CDCLK_320MHz;
-		printk_debug(" Display: 320MHz\n");
+		printk(BIOS_DEBUG, " Display: 320MHz\n");
 	}
 	pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
 
@@ -2050,21 +2050,21 @@
 	offset++;
 #endif
 
-	printk_debug ("Setting Memory Frequency... ");
+	printk(BIOS_DEBUG, "Setting Memory Frequency... ");
 
 	clkcfg = MCHBAR32(CLKCFG);
 
-	printk_debug("CLKCFG=0x%08x, ", clkcfg);
+	printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg);
 
 	clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
 
 	if (sysinfo->mvco4x) {
-		printk_debug("MVCO 4x, ");
+		printk(BIOS_DEBUG, "MVCO 4x, ");
 		clkcfg &= ~(1 << 12);
 	}
 
 	if (sysinfo->clkcfg_bit7) {
-		printk_debug("second VCO, ");
+		printk(BIOS_DEBUG, "second VCO, ");
 
 		clkcfg |= (1 << 7);
 	}
@@ -2077,7 +2077,7 @@
 	}
 
 	if (MCHBAR32(CLKCFG) == clkcfg) {
-		printk_debug ("ok (unchanged)\n");
+		printk(BIOS_DEBUG, "ok (unchanged)\n");
 		return;
 	}
 
@@ -2118,8 +2118,8 @@
 	goto vco_update;
 out:
 
-	printk_debug("CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
-	printk_debug ("ok\n");
+	printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
+	printk(BIOS_DEBUG, "ok\n");
 }
 
 static void sdram_program_clock_crossing(void)
@@ -2222,28 +2222,28 @@
 	};
 #endif
 
-	printk_debug("Programming Clock Crossing...");
+	printk(BIOS_DEBUG, "Programming Clock Crossing...");
 
-	printk_debug("MEM=");
+	printk(BIOS_DEBUG, "MEM=");
 	switch (memclk()) {
-	case 400:	printk_debug("400"); idx += 0; break;
-	case 533:	printk_debug("533"); idx += 2; break;
-	case 667:	printk_debug("667"); idx += 4; break;
-	default: printk_debug("RSVD %x", memclk()); return;
+	case 400:	printk(BIOS_DEBUG, "400"); idx += 0; break;
+	case 533:	printk(BIOS_DEBUG, "533"); idx += 2; break;
+	case 667:	printk(BIOS_DEBUG, "667"); idx += 4; break;
+	default: printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
 	}
 
-	printk_debug(" FSB=");
+	printk(BIOS_DEBUG, " FSB=");
 	switch (fsbclk()) {
-	case 400:	printk_debug("400"); idx += 0; break;
-	case 533:	printk_debug("533"); idx += 6; break;
-	case 667:	printk_debug("667"); idx += 12; break;
-	case 800:	printk_debug("800"); idx += 18; break;
-	case 1066:	printk_debug("1066"); idx += 24; break;
-	default: printk_debug("RSVD %x\n", fsbclk()); return;
+	case 400:	printk(BIOS_DEBUG, "400"); idx += 0; break;
+	case 533:	printk(BIOS_DEBUG, "533"); idx += 6; break;
+	case 667:	printk(BIOS_DEBUG, "667"); idx += 12; break;
+	case 800:	printk(BIOS_DEBUG, "800"); idx += 18; break;
+	case 1066:	printk(BIOS_DEBUG, "1066"); idx += 24; break;
+	default: printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
 	}
 
 	if (command_clock_crossing[idx]==0xffffffff) {
-		printk_debug("Invalid MEM/FSB combination!\n");
+		printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n");
 	}
 
 	MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
@@ -2254,7 +2254,7 @@
 	MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
 	MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
 
-	printk_debug("... ok\n");
+	printk(BIOS_DEBUG, "... ok\n");
 }
 
 static void sdram_disable_fast_dispatch(void)
@@ -2569,7 +2569,7 @@
 #ifdef C2_SELF_REFRESH_DISABLE
 
 	if (integrated_graphics) {
-		printk_debug("C2 self-refresh with IGD\n");
+		printk(BIOS_DEBUG, "C2 self-refresh with IGD\n");
 		MCHBAR16(MIPMC4) = 0x0468;
 		MCHBAR16(MIPMC5) = 0x046c;
 		MCHBAR16(MIPMC6) = 0x046c;
@@ -2728,7 +2728,7 @@
 
 	if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
 			sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
-		printk_debug("one dimm per channel config.. \n");
+		printk(BIOS_DEBUG, "one dimm per channel config.. \n");
 
 		reg32 = MCHBAR32(C0ODT);
 		reg32 &= ~(7 << 28);
@@ -2832,7 +2832,7 @@
 			continue;
 		}
 
-		printk_debug("jedec enable sequence: bank %d\n", i);
+		printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i);
 		switch (i) {
 		case 0:
 			/* Start at address 0 */
@@ -2845,7 +2845,7 @@
 			}
 		default:
 			if (nonzero != -1) {
-				printk_debug("bankaddr from bank size of rank %d\n", nonzero);
+				printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero);
 				bankaddr += sysinfo->banksize[nonzero] <<
 					(sysinfo->interleaved ? 26 : 25);
 				break;
@@ -3010,7 +3010,7 @@
 
 	sdram_detect_errors();
 
-	printk_debug ("Setting up RAM controller.\n");
+	printk(BIOS_DEBUG, "Setting up RAM controller.\n");
 
 	memset(&sysinfo, 0, sizeof(sysinfo));
 
@@ -3131,7 +3131,7 @@
 	reg8 &= ~(1 << 7);
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 
-	printk_debug("RAM initialization finished.\n");
+	printk(BIOS_DEBUG, "RAM initialization finished.\n");
 
 	sdram_setup_processor_side();
 }
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index 846af4f..a912b26 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -67,7 +67,7 @@
 {
 	u32 reg32;
 
-	printk_spew("    set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse);
+	printk(BIOS_SPEW, "    set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse);
 
 	reg32 = MCHBAR32(C0DRT1 + channel_offset);
 	reg32 &= 0xf0ffffff;
@@ -76,7 +76,7 @@
 
 	/* This should never happen: */
 	if (coarse > 0x0f)
-		printk_debug("set_receive_enable: coarse overflow: 0x%02x.\n", coarse);
+		printk(BIOS_DEBUG, "set_receive_enable: coarse overflow: 0x%02x.\n", coarse);
 
 	/* medium control
 	 *
@@ -102,7 +102,7 @@
 
 static int normalize(int channel_offset, u8 * mediumcoarse, u8 * fine)
 {
-	printk_spew("  normalize()\n");
+	printk(BIOS_SPEW, "  normalize()\n");
 
 	if (*fine < 0x80)
 		return 0;
@@ -111,7 +111,7 @@
 	*mediumcoarse += 1;
 
 	if (*mediumcoarse >= 0x40) {
-		printk_debug("Normalize Error\n");
+		printk(BIOS_DEBUG, "Normalize Error\n");
 		return -1;
 	}
 
@@ -129,11 +129,11 @@
 	/* find start of the data phase */
 	u32 reg32;
 
-	printk_spew("  find_preamble()\n");
+	printk(BIOS_SPEW, "  find_preamble()\n");
 
 	do {
 		if (*mediumcoarse < 4) {
-			printk_debug("No Preamble found.\n");
+			printk(BIOS_DEBUG, "No Preamble found.\n");
 			return -1;
 		}
 		*mediumcoarse -= 4;
@@ -146,7 +146,7 @@
 	} while (reg32 & (1 << 19));
 
 	if (!(reg32 & (1 << 18))) {
-		printk_debug("No Preamble found (neither high nor low).\n");
+		printk(BIOS_DEBUG, "No Preamble found (neither high nor low).\n");
 		return -1;
 	}
 
@@ -159,14 +159,14 @@
 
 static int add_quarter_clock(int channel_offset, u8 * mediumcoarse, u8 * fine)
 {
-	printk_spew("  add_quarter_clock() mediumcoarse=%02x fine=%02x\n",
+	printk(BIOS_SPEW, "  add_quarter_clock() mediumcoarse=%02x fine=%02x\n",
 			*mediumcoarse, *fine);
 	if (*fine >= 0x80) {
 		*fine -= 0x80;
 
 		*mediumcoarse += 2;
 		if (*mediumcoarse >= 0x40) {
-			printk_debug("clocks at max.\n");
+			printk(BIOS_DEBUG, "clocks at max.\n");
 			return -1;
 		}
 
@@ -186,7 +186,7 @@
 {
 	u32 rcvenmt;
 
-	printk_spew("  find_strobes_low()\n");
+	printk(BIOS_SPEW, "  find_strobes_low()\n");
 
 	for (;;) {
 		MCHBAR8(C0WL0REOST + channel_offset) = *fine;
@@ -211,7 +211,7 @@
 
 	}
 
-	printk_debug("Could not find low strobe\n");
+	printk(BIOS_DEBUG, "Could not find low strobe\n");
 	return 0;
 }
 
@@ -222,7 +222,7 @@
 	int counter;
 	u32 rcvenmt;
 
-	printk_spew("  find_strobes_edge()\n");
+	printk(BIOS_SPEW, "  find_strobes_edge()\n");
 
 	counter = 8;
 	set_receive_enable(channel_offset, *mediumcoarse & 3,
@@ -257,7 +257,7 @@
 			continue;
 		}
 
-		printk_debug("Could not find rising edge.\n");
+		printk(BIOS_DEBUG, "Could not find rising edge.\n");
 		return -1;
 	}
 
@@ -286,7 +286,7 @@
 	u8 mediumcoarse;
 	u8 fine;
 
-	printk_spew("receive_enable_autoconfig() for channel %d\n",
+	printk(BIOS_SPEW, "receive_enable_autoconfig() for channel %d\n",
 		    channel_offset ? 1 : 0);
 
 	/* Set initial values */
@@ -315,7 +315,7 @@
 	 * It can be removed when the output message is not printed anymore
 	 */
 	if (MCHBAR8(C0WL0REOST + channel_offset) == 0) {
-		printk_debug("Weird. No C%sWL0REOST\n", channel_offset?"1":"0");
+		printk(BIOS_DEBUG, "Weird. No C%sWL0REOST\n", channel_offset?"1":"0");
 	}
 
 	return 0;
diff --git a/src/northbridge/via/cn400/agp.c b/src/northbridge/via/cn400/agp.c
index c9cca61..a302759 100644
--- a/src/northbridge/via/cn400/agp.c
+++ b/src/northbridge/via/cn400/agp.c
@@ -36,7 +36,7 @@
 	int i, j;
 
 	/* Some of this may not be necessary (should be handled by the OS). */
-	printk_debug("Enabling AGP.\n");
+	printk(BIOS_DEBUG, "Enabling AGP.\n");
 
 	/* Allow R/W access to AGP registers. */
 	pci_write_config8(dev, 0x4d, 0x05);
@@ -113,17 +113,17 @@
 	pci_write_config8(dev, 0xc1, 0x02);
 
 #ifdef DEBUG_CN400
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 #endif
 }
@@ -170,7 +170,7 @@
 	u8 reg8;
 	int i, j;
 
-	printk_debug("Entering %s\n", __func__);
+	printk(BIOS_DEBUG, "Entering %s\n", __func__);
 
 	pci_write_config16(dev, 0x4, 0x0107);
 
@@ -208,17 +208,17 @@
 	pci_write_config8(dev, 0x44, 0x34);
 	pci_write_config8(dev, 0x45, 0x72);
 
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 
 }
diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c
index 86dea8d..cd6a2ab 100644
--- a/src/northbridge/via/cn400/northbridge.c
+++ b/src/northbridge/via/cn400/northbridge.c
@@ -41,7 +41,7 @@
 	u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8;
 	int i, j;
 
-	printk_spew("Entering cn400 memctrl_init.\n");
+	printk(BIOS_SPEW, "Entering cn400 memctrl_init.\n");
 	/* vlink mirror */
 	vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
 				    PCI_DEVICE_ID_VIA_CN400_VLINK, 0);
@@ -53,7 +53,7 @@
 	reg16 = (((u16)(ranks - 1) << 9) & 0xFFF0) | 0x01F0;
 
 	pci_write_config16(dev, 0x84, reg16);
-	printk_spew("Low Top Address = 0x%04X\n", reg16);
+	printk(BIOS_SPEW, "Low Top Address = 0x%04X\n", reg16);
 
 	/* Set up the VGA framebuffer size and Base Address   */
 	/* Note dependencies between agp.c and vga.c and here */
@@ -110,20 +110,20 @@
 	pci_write_config8(dev, 0xA0, reg8);
 
 #ifdef DEBUG_CN400
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 #endif
-	printk_spew("Leaving cn400 %s.\n", __func__);
+	printk(BIOS_SPEW, "Leaving cn400 %s.\n", __func__);
 }
 
 static const struct device_operations memctrl_operations = {
@@ -144,7 +144,7 @@
 {
 	struct resource *resource;
 
-	printk_spew("Entering %s.\n", __func__);
+	printk(BIOS_SPEW, "Entering %s.\n", __func__);
 
 	/* Initialize the system wide I/O space constraints. */
 	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
@@ -158,7 +158,7 @@
 	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 	    IORESOURCE_ASSIGNED;
 
-	printk_spew("Leaving %s.\n", __func__);
+	printk(BIOS_SPEW, "Leaving %s.\n", __func__);
 }
 
 static void ram_resource(device_t dev, unsigned long index,
@@ -180,7 +180,7 @@
 {
 	struct resource *res;
 
-	printk_spew("Configuring Via C3 LAPIC Fixed Resource\n");
+	printk(BIOS_SPEW, "Configuring Via C3 LAPIC Fixed Resource\n");
 	/* Fixed LAPIC resource */
 	res = new_resource(dev, 1);
 	res->base = (resource_t) base;
@@ -205,7 +205,7 @@
 	struct resource *min = NULL;
 	u32 tolm;
 
-	printk_spew("Entering CN400 find_pci_tolm\n");
+	printk(BIOS_SPEW, "Entering CN400 find_pci_tolm\n");
 
 	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM,
 			     tolm_test, &min);
@@ -213,7 +213,7 @@
 	if (min && tolm > min->base)
 		tolm = min->base;
 
-	printk_spew("Leaving CN400 find_pci_tolm\n");
+	printk(BIOS_SPEW, "Leaving CN400 find_pci_tolm\n");
 
 	return tolm;
 }
@@ -229,7 +229,7 @@
 	device_t mc_dev;
 	u32 pci_tolm;
 
-	printk_spew("Entering %s.\n", __func__);
+	printk(BIOS_SPEW, "Entering %s.\n", __func__);
 
 	pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
@@ -244,7 +244,7 @@
 		tomk = rambits * 32 * 1024;
 		/* Compute the Top Of Low Memory (TOLM), in Kb. */
 		tolmk = pci_tolm >> 10;
-		printk_spew("tomk is 0x%x, tolmk is 0x%08X\n", tomk, tolmk);
+		printk(BIOS_SPEW, "tomk is 0x%x, tolmk is 0x%08X\n", tomk, tolmk);
 		if (tolmk >= tomk) {
 			/* The PCI hole does does not overlap the memory. */
 			tolmk = tomk;
@@ -254,7 +254,7 @@
 		/* Locate the High Tables at the Top of Low Memory below the Video RAM */
 		high_tables_base = (uint64_t) (tolmk - (CONFIG_VIDEO_MB *1024) - HIGH_TABLES_SIZE) * 1024;
 		high_tables_size = (uint64_t) HIGH_TABLES_SIZE* 1024;
-		printk_spew("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+		printk(BIOS_SPEW, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 #endif
 
 		/* Report the memory regions. */
@@ -267,12 +267,12 @@
 	}
 	assign_resources(&dev->link[0]);
 	
-	printk_spew("Leaving %s.\n", __func__);
+	printk(BIOS_SPEW, "Leaving %s.\n", __func__);
 }
 
 static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max)
 {
-	printk_debug("Entering %s.\n", __func__);
+	printk(BIOS_DEBUG, "Entering %s.\n", __func__);
 
 	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 	return max;
@@ -305,7 +305,7 @@
 
 static void enable_dev(struct device *dev)
 {
-	printk_spew("In cn400 enable_dev for device %s.\n", dev_path(dev));
+	printk(BIOS_SPEW, "In cn400 enable_dev for device %s.\n", dev_path(dev));
 
 	/* Set the operations if it is a special bus type. */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
diff --git a/src/northbridge/via/cn400/vga.c b/src/northbridge/via/cn400/vga.c
index 5a58d17..ac222ff 100644
--- a/src/northbridge/via/cn400/vga.c
+++ b/src/northbridge/via/cn400/vga.c
@@ -52,14 +52,14 @@
 #endif
 
 	temp = (0xffffffff - CONFIG_FALLBACK_SIZE - 0xffff);
-	printk_debug("Copying BOCHS BIOS from 0x%08X	to 0xf000\n", temp);
+	printk(BIOS_DEBUG, "Copying BOCHS BIOS from 0x%08X	to 0xf000\n", temp);
 	/*
 	 * Copy BOCHS BIOS from 4G-CONFIG_FALLBACK_SIZE-64k (in flash) to 0xf0000 (in RAM)
 	 * This is for compatibility with the VGA ROM's BIOS callbacks.
 	 */
 	//memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
 	memcpy(0xf0000, temp, 0x10000);
-	printk_debug("Initializing VGA\n");
+	printk(BIOS_DEBUG, "Initializing VGA\n");
 
 	/* Set memory rate to 200 MHz. */
 	outb(0x3d, CRTM_INDEX);
@@ -79,12 +79,12 @@
 	pci_write_config32(dev, 0x10, 0xf0000008);
 	pci_write_config32(dev, 0x14, 0xf4000000);
 
-	printk_debug("INSTALL REAL-MODE IDT\n");
+	printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n");
 	setup_realmode_idt();
-	printk_debug("DO THE VGA BIOS\n");
+	printk(BIOS_DEBUG, "DO THE VGA BIOS\n");
 	do_vgabios();
 	/* VGA seems to work without this, but crash & burn with it. */
-	// printk_debug("Enable VGA console\n");
+	// printk(BIOS_DEBUG, "Enable VGA console\n");
 	// vga_enable_console();
 
 	/* It's not clear if these need to be programmed before or after
@@ -106,17 +106,17 @@
 	memset(0xf0000, 0, 0x10000);
 
 #ifdef DEBUG_CN400
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 #endif
 }
diff --git a/src/northbridge/via/cn400/vgabios.c b/src/northbridge/via/cn400/vgabios.c
index 9620deb..0b1cff7 100644
--- a/src/northbridge/via/cn400/vgabios.c
+++ b/src/northbridge/via/cn400/vgabios.c
@@ -349,17 +349,17 @@
 	dev = dev_find_class(PCI_CLASS_DISPLAY_VGA<<8 , 0);
 
 	if (!dev) {
-		printk_debug("NO VGA FOUND\n");
+		printk(BIOS_DEBUG, "NO VGA FOUND\n");
 		return;
 	}
-	printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
+	printk(BIOS_DEBUG, "found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
 
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
         rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
-	printk_debug("VGA BIOS ROM base address: %x\n", rom);
+	printk(BIOS_DEBUG, "VGA BIOS ROM base address: %x\n", rom);
 
 	buf = (unsigned char *) rom;
 	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
@@ -371,13 +371,13 @@
 		buf = (unsigned char *) 0xc0000;
 		if (buf[0]==0x55 && buf[1]==0xAA) {
 			busdevfn = (dev->bus->secondary << 8) | dev->path.pci.devfn;
-			printk_debug("bus/devfn = %#x\n", busdevfn);
+			printk(BIOS_DEBUG, "bus/devfn = %#x\n", busdevfn);
 
 		    	real_mode_switch_call_vga(busdevfn);
 		} else
-			printk_debug("Failed to copy VGA BIOS to 0xc0000\n");
+			printk(BIOS_DEBUG, "Failed to copy VGA BIOS to 0xc0000\n");
 	} else 
-		printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
+		printk(BIOS_DEBUG, "BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, 0);
 }
@@ -562,28 +562,28 @@
 	cs = cs_ip >> 16;
 	flags = stackflags;
 	
-	printk_debug("biosint: INT# 0x%lx\n", intnumber);
-	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
+	printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
+	printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
 		      eax, ebx, ecx, edx);
-	printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
 		     ebp, esp, edi, esi);
-	printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
+	printk(BIOS_DEBUG, "biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
 		     ip, cs, flags);
 
 	// cases in a good compiler are just as good as your own tables. 
 	switch (intnumber) {
 	case 0 ... 15:
 		// These are not BIOS service, but the CPU-generated exceptions
-		printk_info("biosint: Oops, exception %u\n", intnumber);
+		printk(BIOS_INFO, "biosint: Oops, exception %u\n", intnumber);
 		if (esp < 0x1000) {
-			printk_debug("Stack contents: ");
+			printk(BIOS_DEBUG, "Stack contents: ");
 			while (esp < 0x1000) {
-				printk_debug("0x%04x ", *(unsigned short *) esp);
+				printk(BIOS_DEBUG, "0x%04x ", *(unsigned short *) esp);
 				esp += 2;
 			}
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
-		printk_debug("biosint: Bailing out\n");
+		printk(BIOS_DEBUG, "biosint: Bailing out\n");
 		// "longjmp"
 		vga_exit();
 		break;
@@ -602,7 +602,7 @@
 				&ebx, &edx, &ecx, &eax, &flags);
 		break;
 	default:
-		printk_info("BIOSINT: Unsupport int #0x%x\n", 
+		printk(BIOS_INFO, "BIOSINT: Unsupport int #0x%x\n", 
 			    intnumber);
 		break;
 	}
@@ -728,7 +728,7 @@
 			// devfn is an int, so we mask it off. 
 			busdevfn = (dev->bus->secondary << 8)
 				| (dev->path.pci.devfn & 0xff);
-			printk_debug("0x%x: return 0x%x\n", func, busdevfn);
+			printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn);
 			*pebx = busdevfn;
 			retval = 0;
 		} else {
@@ -754,7 +754,7 @@
 		reg = *pedi;
 		dev = dev_find_slot(bus, devfn);
 		if (! dev) {
-			printk_debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
+			printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
 			// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
 			*peax = PCIBIOS_BADREG;
 			retval = -1;
@@ -788,14 +788,14 @@
 		
 		if (retval) 
 			retval = PCIBIOS_BADREG;
-		printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+		printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
 			     func, bus, devfn, reg, *pecx);
 		*peax = 0;
 		retval = 0;
 	}
 	break;
 	default:
-		printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
+		printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
 		break;
 	}
 	
diff --git a/src/northbridge/via/cn400/vlink.c b/src/northbridge/via/cn400/vlink.c
index 1542af7..dc574c1 100644
--- a/src/northbridge/via/cn400/vlink.c
+++ b/src/northbridge/via/cn400/vlink.c
@@ -43,7 +43,7 @@
 	u8 reg, reg8;
 	int i, j;
 
-	printk_spew("Entering CN400 %s\n", __func__);
+	printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
 
 	/* Disconnect the VLink Before Changing Settings */
 	reg = pci_read_config8(dev, 0x47);
@@ -107,17 +107,17 @@
 	reg &= ~0x04;
 	pci_write_config8(dev, 0x47, reg);
 
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 #endif
 }
@@ -141,19 +141,19 @@
 	u8 reg8;
 	int i, j;
 
-	printk_spew("Entering CN400 %s\n", __func__);
+	printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
 
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 
 }
@@ -178,19 +178,19 @@
 	u8 reg8;
 	int i, j;
 
-	printk_spew("Entering CN400 %s\n", __func__);
+	printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
 
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 
 }
@@ -214,19 +214,19 @@
 	u8 reg8;
 	int i, j;
 
-	printk_spew("Entering CN400 %s\n", __func__);
+	printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
 
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 
 }
diff --git a/src/northbridge/via/cn700/agp.c b/src/northbridge/via/cn700/agp.c
index 6ae8e78..327fac4 100644
--- a/src/northbridge/via/cn700/agp.c
+++ b/src/northbridge/via/cn700/agp.c
@@ -34,7 +34,7 @@
 	u32 reg32;
 
 	/* Some of this may not be necessary (should be handled by the OS). */
-	printk_debug("Enabling AGP.\n");
+	printk(BIOS_DEBUG, "Enabling AGP.\n");
 
 	/* Allow R/W access to AGP registers. */
 	pci_write_config8(dev, 0x4d, 0x15);
@@ -124,7 +124,7 @@
  */
 static void agp_bridge_init(device_t dev)
 {
-	printk_debug("Setting up AGP bridge device\n");
+	printk(BIOS_DEBUG, "Setting up AGP bridge device\n");
 
 	pci_write_config16(dev, 0x4, 0x0007);
 
diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c
index db0a1cf..2be45f7 100644
--- a/src/northbridge/via/cn700/northbridge.c
+++ b/src/northbridge/via/cn700/northbridge.c
@@ -155,7 +155,7 @@
 	device_t mc_dev;
 	u32 pci_tolm;
 
-	printk_spew("Entering cn700 pci_domain_set_resources.\n");
+	printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n");
 
 	pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
@@ -177,7 +177,7 @@
 		}
 
 		tomk = rambits * 64 * 1024;
-		printk_spew("tomk is 0x%x\n", tomk);
+		printk(BIOS_SPEW, "tomk is 0x%x\n", tomk);
 		/* Compute the Top Of Low Memory (TOLM), in Kb. */
 		tolmk = pci_tolm >> 10;
 		if (tolmk >= tomk) {
@@ -188,7 +188,7 @@
 #if CONFIG_WRITE_HIGH_TABLES == 1
 		high_tables_base = (tolmk - CONFIG_VIDEO_MB * 1024 - HIGH_TABLES_SIZE) * 1024;
 		high_tables_size = HIGH_TABLES_SIZE * 1024;
-		printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+		printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 #endif
 
 		/* Report the memory regions. */
@@ -229,7 +229,7 @@
 
 static void enable_dev(struct device *dev)
 {
-	printk_spew("In cn700 enable_dev for device %s.\n", dev_path(dev));
+	printk(BIOS_SPEW, "In cn700 enable_dev for device %s.\n", dev_path(dev));
 
 	/* Set the operations if it is a special bus type. */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c
index e4f9d93..283f23d 100644
--- a/src/northbridge/via/cn700/vga.c
+++ b/src/northbridge/via/cn700/vga.c
@@ -54,7 +54,7 @@
 	 */
 	memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
 
-	printk_debug("Initializing VGA\n");
+	printk(BIOS_DEBUG, "Initializing VGA\n");
 
 	/* Set memory rate to 200 MHz. */
 	outb(0x3d, CRTM_INDEX);
@@ -74,12 +74,12 @@
 	pci_write_config32(dev, 0x10, 0xf4000008);
 	pci_write_config32(dev, 0x14, 0xfb000000);
 
-	printk_debug("INSTALL REAL-MODE IDT\n");
+	printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n");
 	setup_realmode_idt();
-	printk_debug("DO THE VGA BIOS\n");
+	printk(BIOS_DEBUG, "DO THE VGA BIOS\n");
 	do_vgabios();
 	/* VGA seems to work without this, but crash & burn with it. */
-	// printk_debug("Enable VGA console\n");
+	// printk(BIOS_DEBUG, "Enable VGA console\n");
 	// vga_enable_console();
 
 	/* It's not clear if these need to be programmed before or after
diff --git a/src/northbridge/via/cn700/vgabios.c b/src/northbridge/via/cn700/vgabios.c
index 82a2bab..1b3a9f0 100644
--- a/src/northbridge/via/cn700/vgabios.c
+++ b/src/northbridge/via/cn700/vgabios.c
@@ -349,17 +349,17 @@
 	dev = dev_find_class(PCI_CLASS_DISPLAY_VGA<<8 , 0);
 
 	if (!dev) {
-		printk_debug("NO VGA FOUND\n");
+		printk(BIOS_DEBUG, "NO VGA FOUND\n");
 		return;
 	}
-	printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
+	printk(BIOS_DEBUG, "found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
 
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
 	rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
-	printk_debug("rom base, size: %x\n", rom);
+	printk(BIOS_DEBUG, "rom base, size: %x\n", rom);
 
 	buf = (unsigned char *) rom;
 	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
@@ -371,13 +371,13 @@
 		buf = (unsigned char *) 0xc0000;
 		if (buf[0]==0x55 && buf[1]==0xAA) {
 			busdevfn = (dev->bus->secondary << 8) | dev->path.pci.devfn;
-			printk_debug("bus/devfn = %#x\n", busdevfn);
+			printk(BIOS_DEBUG, "bus/devfn = %#x\n", busdevfn);
 
 		    	real_mode_switch_call_vga(busdevfn);
 		} else
-			printk_debug("Failed to copy VGA BIOS to 0xc0000\n");
+			printk(BIOS_DEBUG, "Failed to copy VGA BIOS to 0xc0000\n");
 	} else 
-		printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
+		printk(BIOS_DEBUG, "BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, 0);
 }
@@ -562,28 +562,28 @@
 	cs = cs_ip >> 16;
 	flags = stackflags;
 	
-	printk_debug("biosint: INT# 0x%lx\n", intnumber);
-	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
+	printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
+	printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
 		      eax, ebx, ecx, edx);
-	printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
 		     ebp, esp, edi, esi);
-	printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
+	printk(BIOS_DEBUG, "biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
 		     ip, cs, flags);
 
 	// cases in a good compiler are just as good as your own tables. 
 	switch (intnumber) {
 	case 0 ... 15:
 		// These are not BIOS service, but the CPU-generated exceptions
-		printk_info("biosint: Oops, exception %u\n", intnumber);
+		printk(BIOS_INFO, "biosint: Oops, exception %u\n", intnumber);
 		if (esp < 0x1000) {
-			printk_debug("Stack contents: ");
+			printk(BIOS_DEBUG, "Stack contents: ");
 			while (esp < 0x1000) {
-				printk_debug("0x%04x ", *(unsigned short *) esp);
+				printk(BIOS_DEBUG, "0x%04x ", *(unsigned short *) esp);
 				esp += 2;
 			}
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
-		printk_debug("biosint: Bailing out\n");
+		printk(BIOS_DEBUG, "biosint: Bailing out\n");
 		// "longjmp"
 		vga_exit();
 		break;
@@ -602,7 +602,7 @@
 				&ebx, &edx, &ecx, &eax, &flags);
 		break;
 	default:
-		printk_info("BIOSINT: Unsupport int #0x%x\n", 
+		printk(BIOS_INFO, "BIOSINT: Unsupport int #0x%x\n", 
 			    intnumber);
 		break;
 	}
@@ -728,7 +728,7 @@
 			// devfn is an int, so we mask it off. 
 			busdevfn = (dev->bus->secondary << 8)
 				| (dev->path.pci.devfn & 0xff);
-			printk_debug("0x%x: return 0x%x\n", func, busdevfn);
+			printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn);
 			*pebx = busdevfn;
 			retval = 0;
 		} else {
@@ -754,7 +754,7 @@
 		reg = *pedi;
 		dev = dev_find_slot(bus, devfn);
 		if (! dev) {
-			printk_debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
+			printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
 			// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
 			*peax = PCIBIOS_BADREG;
 			retval = -1;
@@ -788,14 +788,14 @@
 		
 		if (retval) 
 			retval = PCIBIOS_BADREG;
-		printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+		printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
 			     func, bus, devfn, reg, *pecx);
 		*peax = 0;
 		retval = 0;
 	}
 	break;
 	default:
-		printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
+		printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
 		break;
 	}
 	
diff --git a/src/northbridge/via/cx700/cx700_lpc.c b/src/northbridge/via/cx700/cx700_lpc.c
index 94383872..d6495ab 100644
--- a/src/northbridge/via/cx700/cx700_lpc.c
+++ b/src/northbridge/via/cx700/cx700_lpc.c
@@ -56,7 +56,7 @@
 
 static void pci_routing_fixup(struct device *dev)
 {
-	printk_debug("%s: device is %p\n", __FUNCTION__, dev);
+	printk(BIOS_DEBUG, "%s: device is %p\n", __FUNCTION__, dev);
 
 	/* set up PCI IRQ routing */
 	pci_write_config8(dev, 0x55, pci_irqs[0] << 4);
@@ -64,17 +64,17 @@
 	pci_write_config8(dev, 0x57, pci_irqs[3] << 4);
 
 	/* Assigning IRQs */
-	printk_debug("Setting up USB interrupts.\n");
+	printk(BIOS_DEBUG, "Setting up USB interrupts.\n");
 	pci_assign_irqs(0, 0x10, pin_to_irq(usb_pins));
 
-	printk_debug("Setting up VGA interrupts.\n");
+	printk(BIOS_DEBUG, "Setting up VGA interrupts.\n");
 	pci_assign_irqs(1, 0x00, pin_to_irq(vga_pins));
 
-	printk_debug("Setting up PCI slot interrupts.\n");
+	printk(BIOS_DEBUG, "Setting up PCI slot interrupts.\n");
 	pci_assign_irqs(2, 0x04, pin_to_irq(slot_pins));
 	// more?
 
-	printk_debug("Setting up AC97 interrupts.\n");
+	printk(BIOS_DEBUG, "Setting up AC97 interrupts.\n");
 	pci_assign_irqs(0x80, 0x1, pin_to_irq(ac97_pins));
 }
 
@@ -169,7 +169,7 @@
 {
 	unsigned char enables;
 
-	printk_debug("VIA CX700 LPC bridge init\n");
+	printk(BIOS_DEBUG, "VIA CX700 LPC bridge init\n");
 
 	// enable the internal I/O decode
 	enables = pci_read_config8(dev, 0x6C);
diff --git a/src/northbridge/via/cx700/cx700_sata.c b/src/northbridge/via/cx700/cx700_sata.c
index 8931266..993b05a 100644
--- a/src/northbridge/via/cx700/cx700_sata.c
+++ b/src/northbridge/via/cx700/cx700_sata.c
@@ -46,7 +46,7 @@
 {
 	u8 reg8;
 
-	printk_debug("Configuring VIA SATA & EIDE Controller\n");
+	printk(BIOS_DEBUG, "Configuring VIA SATA & EIDE Controller\n");
 
 	/* Class IDE Disk, instead of RAID controller */
 	reg8 = pci_read_config8(dev, 0x45);
@@ -57,7 +57,7 @@
 	pci_write_config8(dev, 0x45, reg8);
 
 #if defined(DISABLE_SATA) && (DISABLE_SATA == 1)
-	printk_info("Disabling SATA (Primary Channel)\n");
+	printk(BIOS_INFO, "Disabling SATA (Primary Channel)\n");
 	/* Disable SATA channels */
 	pci_write_config8(dev, 0x40, 0x00);
 #else
@@ -132,12 +132,12 @@
 	reg8 &= ~0xa0;
 	pci_write_config8(dev, 0x42, reg8);
 	reg8 = pci_read_config8(dev, 0x42);
-	printk_debug("Reg 0x42 read back as 0x%x\n", reg8);
+	printk(BIOS_DEBUG, "Reg 0x42 read back as 0x%x\n", reg8);
 
 	/* Support Staggered Spin-Up */
 	reg8 = pci_read_config8(dev, 0xb9);
 	if ((reg8 & 0x8) == 0) {
-		printk_debug("start OOB sequence on both drives\n");
+		printk(BIOS_DEBUG, "start OOB sequence on both drives\n");
 		reg8 |= 0x30;
 		pci_write_config8(dev, 0xb9, reg8);
 	}
diff --git a/src/northbridge/via/cx700/cx700_usb.c b/src/northbridge/via/cx700/cx700_usb.c
index b2dc482..a851894 100644
--- a/src/northbridge/via/cx700/cx700_usb.c
+++ b/src/northbridge/via/cx700/cx700_usb.c
@@ -28,7 +28,7 @@
 	u8 reg8;
 
 	/* USB Specification says the device must be Bus Master */
-	printk_debug("UHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
 
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
@@ -37,7 +37,7 @@
 	reg8 |= (1 << 0);
 	pci_write_config8(dev, 0xca, reg8);
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static struct device_operations usb_ops = {
diff --git a/src/northbridge/via/cx700/cx700_vga.c b/src/northbridge/via/cx700/cx700_vga.c
index bcb7d9e..c259b37 100644
--- a/src/northbridge/via/cx700/cx700_vga.c
+++ b/src/northbridge/via/cx700/cx700_vga.c
@@ -49,7 +49,7 @@
 {
 	device_t dev;
 
-	printk_debug("write_protect_vgabios\n");
+	printk(BIOS_DEBUG, "write_protect_vgabios\n");
 
 	dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
 	if (dev)
@@ -64,7 +64,7 @@
 {
 	u8 reg8;
 
-	printk_debug("Initializing VGA...\n");
+	printk(BIOS_DEBUG, "Initializing VGA...\n");
 
 	//*
 	pci_write_config8(dev, 0x04, 0x07);
@@ -75,10 +75,10 @@
 	pci_write_config8(dev, 0x3c, 0x0b);
 	//*/
 
-	printk_debug("Executing VGA option rom in real mode\n");
+	printk(BIOS_DEBUG, "Executing VGA option rom in real mode\n");
 	setup_realmode_idt();
 	do_vgabios();
-	printk_debug("Enable VGA console\n");
+	printk(BIOS_DEBUG, "Enable VGA console\n");
 	vga_enable_console();
 
 	/* It's not clear if these need to be programmed before or after
diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c
index b08dc17..6a69d43 100644
--- a/src/northbridge/via/cx700/northbridge.c
+++ b/src/northbridge/via/cx700/northbridge.c
@@ -119,7 +119,7 @@
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 	high_tables_size = HIGH_TABLES_SIZE* 1024;
-	printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+	printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 #endif
 
 	/* Report the memory regions */
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index e0277f2..d28b8e3 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -26,7 +26,7 @@
 
 /* Debugging macros. */
 #if CONFIG_DEBUG_RAM_SETUP
-#define PRINTK_DEBUG(x...)      printk_debug(x)
+#define PRINTK_DEBUG(x...)      printk(BIOS_DEBUG, x)
 #else
 #define PRINTK_DEBUG(x...)
 #endif
@@ -105,9 +105,9 @@
 #define REGISTERPRESET(bus,dev,fun,bdfspec) \
 	{ u8 i, reg; \
 		for (i=0; i<(sizeof((bdfspec))/sizeof(struct regmask)); i++) { \
-			printk_debug("Writing bus " #bus " dev " #dev " fun " #fun " register "); \
-			printk_debug("%02x", (bdfspec)[i].reg); \
-			printk_debug("\n"); \
+			printk(BIOS_DEBUG, "Writing bus " #bus " dev " #dev " fun " #fun " register "); \
+			printk(BIOS_DEBUG, "%02x", (bdfspec)[i].reg); \
+			printk(BIOS_DEBUG, "\n"); \
 			reg = pci_read_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg); \
 			reg &= (bdfspec)[i].mask; \
 			reg |= (bdfspec)[i].val; \
@@ -184,7 +184,7 @@
 
 	regs = pci_read_config8(MEMCTRL, 0x6c);
 	if (regs & (1 << 6))
-		printk_debug("DDR2 Detected.\n");
+		printk(BIOS_DEBUG, "DDR2 Detected.\n");
 	else
 		die("ERROR: DDR1 memory detected but not supported by coreboot.\n");
 
@@ -201,25 +201,25 @@
 	/* SPD 9 SDRAM Cycle Time */
 	GET_SPD(dimm, spds, regs, 9);
 
-	printk_debug("\nDDRII ");
+	printk(BIOS_DEBUG, "\nDDRII ");
 	if (spds <= 0x3d) {
-		printk_debug("533");
+		printk(BIOS_DEBUG, "533");
 		val = DDRII_533;
 		t = 38;
 	} else if (spds <= 0x50) {
-		printk_debug("400");
+		printk(BIOS_DEBUG, "400");
 		val = DDRII_400;
 		t = 50;
 	} else if (spds <= 0x60) {
-		printk_debug("333");
+		printk(BIOS_DEBUG, "333");
 		val = DDRII_333;
 		t = 60;
 	} else if (spds <= 0x75) {
-		printk_debug("266");
+		printk(BIOS_DEBUG, "266");
 		val = DDRII_266;
 		t = 75;
 	} else {
-		printk_debug("200");
+		printk(BIOS_DEBUG, "200");
 		val = DDRII_200;
 		t = 100;
 	}
@@ -259,45 +259,45 @@
 	/* SPD 9 18 23 25 CAS Latency NB3DRAM_REG62[2:0] */
 	/* Read SPD byte 18 CAS Latency */
 	GET_SPD(dimm, spds, regs, SPD_CAS_LAT);
-	printk_debug("\nCAS Supported ");
+	printk(BIOS_DEBUG, "\nCAS Supported ");
 	if (spds & SPD_CAS_LAT_2)
-		printk_debug("2 ");
+		printk(BIOS_DEBUG, "2 ");
 	if (spds & SPD_CAS_LAT_3)
-		printk_debug("3 ");
+		printk(BIOS_DEBUG, "3 ");
 	if (spds & SPD_CAS_LAT_4)
-		printk_debug("4 ");
+		printk(BIOS_DEBUG, "4 ");
 	if (spds & SPD_CAS_LAT_5)
-		printk_debug("5 ");
+		printk(BIOS_DEBUG, "5 ");
 	if (spds & SPD_CAS_LAT_6)
-		printk_debug("6");
+		printk(BIOS_DEBUG, "6");
 
 	/* We don't consider CAS = 6, because CX700 doesn't support it */
-	printk_debug("\n CAS:");
+	printk(BIOS_DEBUG, "\n CAS:");
 	if (spds & SPD_CAS_LAT_5) {
-		printk_debug("Starting at CL5");
+		printk(BIOS_DEBUG, "Starting at CL5");
 		val = 0x3;
 		/* See whether we can improve it */
 		GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_1);
 		if ((spds & SPD_CAS_LAT_4) && (tmp < 0x50)) {
-			printk_debug("\n... going to CL4");
+			printk(BIOS_DEBUG, "\n... going to CL4");
 			val = 0x2;
 		}
 		GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_2);
 		if ((spds & SPD_CAS_LAT_3) && (tmp < 0x50)) {
-			printk_debug("\n... going to CL3");
+			printk(BIOS_DEBUG, "\n... going to CL3");
 			val = 0x1;
 		}
 	} else {
-		printk_debug("Starting at CL4");
+		printk(BIOS_DEBUG, "Starting at CL4");
 		val = 0x2;
 		GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_1);
 		if ((spds & SPD_CAS_LAT_3) && (tmp < 0x50)) {
-			printk_debug("\n... going to CL3");
+			printk(BIOS_DEBUG, "\n... going to CL3");
 			val = 0x1;
 		}
 		GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_2);
 		if ((spds & SPD_CAS_LAT_2) && (tmp < 0x50)) {
-			printk_debug("\n... going to CL2");
+			printk(BIOS_DEBUG, "\n... going to CL2");
 			val = 0x0;
 		}
 	}
@@ -308,7 +308,7 @@
 
 	/* SPD 27 Trp NB3DRAM_REG64[3:2] */
 	GET_SPD(dimm, spds, regs, SPD_TRP);
-	printk_debug("\nTrp %d", spds);
+	printk(BIOS_DEBUG, "\nTrp %d", spds);
 	spds >>= 2;
 	for (val = 2; val <= 5; val++) {
 		if (spds <= (val * t / 10)) {
@@ -324,7 +324,7 @@
 
 	/* SPD 29 Trcd NB3DRAM_REG64[7:6] */
 	GET_SPD(dimm, spds, regs, SPD_TRCD);
-	printk_debug("\nTrcd %d", spds);
+	printk(BIOS_DEBUG, "\nTrcd %d", spds);
 	spds >>= 2;
 	for (val = 2; val <= 5; val++) {
 		if (spds <= (val * t / 10)) {
@@ -340,7 +340,7 @@
 
 	/* SPD 30 Tras NB3DRAM_REG62[7:4] */
 	GET_SPD(dimm, spds, regs, SPD_TRAS);
-	printk_debug("\nTras %d", spds);
+	printk(BIOS_DEBUG, "\nTras %d", spds);
 	for (val = 5; val <= 20; val++) {
 		if (spds <= (val * t / 10)) {
 			val = val - 5;
@@ -355,7 +355,7 @@
 
 	/* SPD 42 SPD 40 Trfc NB3DRAM_REG61[5:0] */
 	GET_SPD(dimm, spds, regs, SPD_TRFC);
-	printk_debug("\nTrfc %d", spds);
+	printk(BIOS_DEBUG, "\nTrfc %d", spds);
 	tmp = spds;
 	GET_SPD(dimm, spds, regs, SPD_EX_TRC_TRFC);
 	if (spds & 0x1)
@@ -382,7 +382,7 @@
 		}
 	}
 	val <<= 6;
-	printk_debug("\nTrrd val = 0x%x", val);
+	printk(BIOS_DEBUG, "\nTrrd val = 0x%x", val);
 	regs = pci_read_config8(MEMCTRL, 0x63);
 	regs &= ~0xc0;
 	regs |= val;
@@ -397,7 +397,7 @@
 		}
 	}
 	val <<= 6;
-	printk_debug("\nTwr val = 0x%x", val);
+	printk(BIOS_DEBUG, "\nTwr val = 0x%x", val);
 
 	regs = pci_read_config8(MEMCTRL, 0x61);
 	regs &= ~0xc0;
@@ -407,13 +407,13 @@
 	/* SPD 37 Twtr NB3DRAM_REG63[1] */
 	GET_SPD(dimm, spds, regs, SPD_TWTR);
 	spds >>= 2;
-	printk_debug("\nTwtr 0x%x", spds);
+	printk(BIOS_DEBUG, "\nTwtr 0x%x", spds);
 	if (spds <= (t * 2 / 10))
 		val = 0;
 	else
 		val = 1;
 	val <<= 1;
-	printk_debug("\nTwtr val = 0x%x", val);
+	printk(BIOS_DEBUG, "\nTwtr val = 0x%x", val);
 
 	regs = pci_read_config8(MEMCTRL, 0x63);
 	regs &= ~0x2;
@@ -423,13 +423,13 @@
 	/* SPD 38 Trtp NB3DRAM_REG63[3] */
 	GET_SPD(dimm, spds, regs, SPD_TRTP);
 	spds >>= 2;
-	printk_debug("\nTrtp 0x%x", spds);
+	printk(BIOS_DEBUG, "\nTrtp 0x%x", spds);
 	if (spds <= (t * 2 / 10))
 		val = 0;
 	else
 		val = 1;
 	val <<= 3;
-	printk_debug("\nTrtp val = 0x%x", val);
+	printk(BIOS_DEBUG, "\nTrtp val = 0x%x", val);
 
 	regs = pci_read_config8(MEMCTRL, 0x63);
 	regs &= ~0x8;
@@ -534,7 +534,7 @@
 			val += spds;
 		}
 	}
-	printk_debug("\nchip #%d", val);
+	printk(BIOS_DEBUG, "\nchip #%d", val);
 	if (val > 18)
 		regs = 0xdb;
 	else
@@ -852,7 +852,7 @@
 	i |= DDR2_Twr_table[val];
 	read32(i);
 
-	printk_debug("MRS = %08x\n", i);
+	printk(BIOS_DEBUG, "MRS = %08x\n", i);
 
 	udelay(15);
 
@@ -1073,7 +1073,7 @@
 		else
 			sdram_clear_vr_addr(ctrl, i);
 	}
-	printk_debug("\nDQSI Low %08x", dl);
+	printk(BIOS_DEBUG, "\nDQSI Low %08x", dl);
 	for (dh = dl; dh < 0x3f; dh += 2) {
 		reg8 = dh & 0x3f;
 		reg8 |= 0x80;	/* Set Manual Mode */
@@ -1106,7 +1106,7 @@
 			break;
 		}
 	}
-	printk_debug("\nDQSI High %02x", dh);
+	printk(BIOS_DEBUG, "\nDQSI High %02x", dh);
 	pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_CHA_DQSI_LOW_REG, dl);
 	pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_CHA_DQSI_HIGH_REG, dh);
 	reg8 = pci_read_config8(MEMCTRL, 0X90) & 0X7;
diff --git a/src/northbridge/via/cx700/vgabios.c b/src/northbridge/via/cx700/vgabios.c
index 042d99e..72b841f 100644
--- a/src/northbridge/via/cx700/vgabios.c
+++ b/src/northbridge/via/cx700/vgabios.c
@@ -315,10 +315,10 @@
 	dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0);
 
 	if (!dev) {
-		printk_debug("NO VGA FOUND\n");
+		printk(BIOS_DEBUG, "NO VGA FOUND\n");
 		return;
 	}
-	printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
+	printk(BIOS_DEBUG, "found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
 
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
@@ -326,7 +326,7 @@
 #warning ROM address hardcoded to 512K
 	rom = (unsigned int)cbfs_load_optionrom(dev->vendor, dev->device, 0); 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom | 1);
-	printk_debug("rom base, size: %x\n", rom);
+	printk(BIOS_DEBUG, "rom base, size: %x\n", rom);
 
 	buf = (unsigned char *)rom;
 	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
@@ -339,13 +339,13 @@
 		if (buf[0] == 0x55 && buf[1] == 0xAA) {
 			busdevfn =
 			    (dev->bus->secondary << 8) | dev->path.pci.devfn;
-			printk_debug("bus/devfn = %#x\n", busdevfn);
+			printk(BIOS_DEBUG, "bus/devfn = %#x\n", busdevfn);
 
 			real_mode_switch_call_vga(busdevfn);
 		} else
-			printk_debug("Failed to copy VGA BIOS to 0xc0000\n");
+			printk(BIOS_DEBUG, "Failed to copy VGA BIOS to 0xc0000\n");
 	} else
-		printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
+		printk(BIOS_DEBUG, "BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, 0);
 }
@@ -512,28 +512,28 @@
 	cs = cs_ip >> 16;
 	flags = stackflags;
 
-	printk_debug("biosint: INT# 0x%lx\n", intnumber);
-	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
+	printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
 		     eax, ebx, ecx, edx);
-	printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
 		     ebp, esp, edi, esi);
-	printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
+	printk(BIOS_DEBUG, "biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
 		     ip, cs, flags);
 
 	// cases in a good compiler are just as good as your own tables. 
 	switch (intnumber) {
 	case 0 ... 15:
 		// These are not BIOS service, but the CPU-generated exceptions
-		printk_info("biosint: Oops, exception %u\n", intnumber);
+		printk(BIOS_INFO, "biosint: Oops, exception %u\n", intnumber);
 		if (esp < 0x1000) {
-			printk_debug("Stack contents: ");
+			printk(BIOS_DEBUG, "Stack contents: ");
 			while (esp < 0x1000) {
-				printk_debug("0x%04x ", *(unsigned short *)esp);
+				printk(BIOS_DEBUG, "0x%04x ", *(unsigned short *)esp);
 				esp += 2;
 			}
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
-		printk_debug("biosint: Bailing out\n");
+		printk(BIOS_DEBUG, "biosint: Bailing out\n");
 		// "longjmp"
 		vga_exit();
 		break;
@@ -552,7 +552,7 @@
 				  &ebx, &edx, &ecx, &eax, &flags);
 		break;
 	default:
-		printk_info("BIOSINT: Unsupport int #0x%x\n", intnumber);
+		printk(BIOS_INFO, "BIOSINT: Unsupport int #0x%x\n", intnumber);
 		break;
 	}
 	if (ret)
@@ -669,7 +669,7 @@
 				// devfn is an int, so we mask it off. 
 				busdevfn = (dev->bus->secondary << 8)
 				    | (dev->path.pci.devfn & 0xff);
-				printk_debug("0x%x: return 0x%x\n", func,
+				printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func,
 					     busdevfn);
 				*pebx = busdevfn;
 				retval = 0;
@@ -696,8 +696,7 @@
 			reg = *pedi;
 			dev = dev_find_slot(bus, devfn);
 			if (!dev) {
-				printk_debug
-				    ("0x%x: BAD DEVICE bus %d devfn 0x%x\n",
+				printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n",
 				     func, bus, devfn);
 				// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
 				*peax = PCIBIOS_BADREG;
@@ -732,15 +731,14 @@
 
 			if (retval)
 				retval = PCIBIOS_BADREG;
-			printk_debug
-			    ("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+			printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
 			     func, bus, devfn, reg, *pecx);
 			*peax = 0;
 			retval = 0;
 		}
 		break;
 	default:
-		printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
+		printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
 		break;
 	}
 
diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index d56456e..5af7836 100644
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -20,7 +20,7 @@
  */
 static void northbridge_init(device_t dev) 
 {
-	printk_spew("VT8601 random fixup ...\n");
+	printk(BIOS_SPEW, "VT8601 random fixup ...\n");
 	pci_write_config8(dev, 0x70, 0xc0);
 	pci_write_config8(dev, 0x71, 0x88);
 	pci_write_config8(dev, 0x72, 0xec);
@@ -117,10 +117,10 @@
 			if (reg > rambits)
 				rambits = reg;
 			if (reg < rambits)
-				printk_err("ERROR! register 0x%x is not set!\n", 
+				printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", 
 					ramregs[i]);
 		}
-		printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
+		printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
 		tomk = rambits*8*1024;
 		/* Compute the top of Low memory */
 		tolmk = pci_tolm >> 10;
@@ -133,7 +133,7 @@
 #if CONFIG_WRITE_HIGH_TABLES == 1
 		high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 		high_tables_size = HIGH_TABLES_SIZE* 1024;
-		printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+		printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 #endif
 
 		/* Report the memory regions */
diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
index 15910fe..fd1c76e 100644
--- a/src/northbridge/via/vt8623/northbridge.c
+++ b/src/northbridge/via/vt8623/northbridge.c
@@ -27,7 +27,7 @@
 	unsigned long fb;
 	unsigned char c;
 
-	printk_debug("VT8623 random fixup ...\n");
+	printk(BIOS_DEBUG, "VT8623 random fixup ...\n");
 	pci_write_config8(dev,  0x0d, 0x08);
 	pci_write_config8(dev,  0x70, 0x82);
 	pci_write_config8(dev,  0x71, 0xc8);
@@ -48,7 +48,7 @@
 		 */
 		//fb = pci_read_config32(dev, 0x10);       /* Base addres of framebuffer */
 		fb = 0xd0000000;
-		printk_debug("Frame buffer at %8x\n",fb);
+		printk(BIOS_DEBUG, "Frame buffer at %8x\n",fb);
 
 		c = pci_read_config8(dev, 0xe1) & 0xf0;  /* size of vga */
 		c |= fb>>28;  /* upper nibble of frame buffer address */
@@ -77,7 +77,7 @@
 
 static void agp_init(device_t dev)
 {
-	printk_debug("VT8623 AGP random fixup ...\n");
+	printk(BIOS_DEBUG, "VT8623 AGP random fixup ...\n");
 
 	pci_write_config8(dev, 0x3e, 0x0c);
 	pci_write_config8(dev, 0x40, 0x83);
@@ -107,7 +107,7 @@
 //	unsigned long fb;
 	msr_t clocks1,clocks2,instructions,setup;
 
-	printk_debug("VGA random fixup ...\n");
+	printk(BIOS_DEBUG, "VGA random fixup ...\n");
 	pci_write_config8(dev, 0x04, 0x07);
 	pci_write_config8(dev, 0x0d, 0x20);
 	pci_write_config32(dev,0x10,0xd8000008);
@@ -131,24 +131,24 @@
 	//clocks2 = rdmsr(0x10);
 	//instructions = rdmsr(0xc2);
 	
-	printk_debug("Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
-	printk_debug("Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
-	printk_debug("Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
+	printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
+	printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
+	printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
 
 #else
 
 	/* code to make vga init run in real mode - does work but against the current coreboot philosophy */
-	printk_debug("INSTALL REAL-MODE IDT\n");
+	printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n");
         setup_realmode_idt();
-        printk_debug("DO THE VGA BIOS\n");
+        printk(BIOS_DEBUG, "DO THE VGA BIOS\n");
         do_vgabios();
 
 	//clocks2 = rdmsr(0x10);
 	//instructions = rdmsr(0xc2);
 	
-	//printk_debug("Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
-	//printk_debug("Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
-	//printk_debug("Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
+	//printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
+	//printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
+	//printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
 
         vga_enable_console();
 	
@@ -229,7 +229,7 @@
 	device_t mc_dev;
         uint32_t pci_tolm;
 
-	printk_spew("Entering vt8623 pci_domain_set_resources.\n");
+	printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n");
 
         pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev->link[0].children;
@@ -250,10 +250,10 @@
 			if (reg > rambits)
 				rambits = reg;
 			if (reg < rambits)
-				printk_err("ERROR! register 0x%x is not set!\n", 
+				printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", 
 					ramregs[i]);
 		}
-		printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
+		printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
 		tomk = rambits*16*1024 - 32768;
 		/* Compute the top of Low memory */
 		tolmk = pci_tolm >> 10;
@@ -266,7 +266,7 @@
 #if CONFIG_WRITE_HIGH_TABLES == 1
 		high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 		high_tables_size = HIGH_TABLES_SIZE* 1024;
-		printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+		printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 #endif
 
 		/* Report the memory regions */
@@ -304,7 +304,7 @@
 
 static void enable_dev(struct device *dev)
 {
-	printk_spew("In vt8623 enable_dev for device %s.\n", dev_path(dev));
+	printk(BIOS_SPEW, "In vt8623 enable_dev for device %s.\n", dev_path(dev));
 
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c
index c04da9c..08d3c95 100644
--- a/src/northbridge/via/vx800/examples/chipset_init.c
+++ b/src/northbridge/via/vx800/examples/chipset_init.c
@@ -261,7 +261,7 @@
 
 	// Get SB Revision
 	sbchiprev = pci_rawread_config8(rawdevice, 0xf6);
-	printk_debug("SB chip revision =%x\n", sbchiprev);
+	printk(BIOS_DEBUG, "SB chip revision =%x\n", sbchiprev);
 
 	// Fill Register Table
 	via_pci_inittable(sbchiprev, mSbStage1InitTbl);
@@ -279,7 +279,7 @@
 	u32 subid = 0;
 	rawdevice = PCI_RAWDEV(0, 0, 4);
 	nbchiprev = pci_rawread_config8(rawdevice, 0xf6);
-	printk_debug("NB chip revision =%x\n", nbchiprev);
+	printk(BIOS_DEBUG, "NB chip revision =%x\n", nbchiprev);
 
 	via_pci_inittable(nbchiprev, mNbStage2InitTable);
 
@@ -414,7 +414,7 @@
 		// Get Chipset Revision
 		EHCIRevision =
 		    pci_rawread_config8(PCI_RAWDEV(0, 0x10, 4), 0xF6);
-		printk_debug("EHCI Revision =%x\n", EHCIRevision);
+		printk(BIOS_DEBUG, "EHCI Revision =%x\n", EHCIRevision);
 		via_pci_inittable(EHCIRevision, mEHCIInitTable);
 	}
 }
@@ -567,7 +567,7 @@
 
 	rawdevice = PCI_RAWDEV(0, 11, 0);
 	sbchiprev = pci_rawread_config8(rawdevice, 0xf6);
-	printk_debug("SB chip revision =%x\n", sbchiprev);
+	printk(BIOS_DEBUG, "SB chip revision =%x\n", sbchiprev);
 
 	//SBBasicInit
 	via_pci_inittable(sbchiprev, mBusControllerInitTable);
@@ -592,7 +592,7 @@
 
 void init_VIA_chipset(void)
 {
-	printk_debug("In: init_VIA_chipset\n");
+	printk(BIOS_DEBUG, "In: init_VIA_chipset\n");
 	//1.nbstage1 is done in raminit.
 	//2.sbstage1
 	AcpiInit();
@@ -604,7 +604,7 @@
 
 	//5.open hdac
 	pci_rawmodify_config32(PCI_RAWDEV(0, 0x11, 7), 0xd1, 0, 0x04);
-	printk_debug("End: init_VIA_chipset\n");
+	printk(BIOS_DEBUG, "End: init_VIA_chipset\n");
 }
 
 /**
@@ -630,7 +630,7 @@
 
 	u8 y, x;
 	init_VIA_chipset();
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 #if 0
 
@@ -653,90 +653,90 @@
 	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x00, 0x76);//open all usb and usb mode
 	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0x76);//close all usb
 
-	printk_info("=================SB 50h=%02x \n",
+	printk(BIOS_INFO, "=================SB 50h=%02x \n",
 		    pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50));
 
 
 	/* FIXME: Is there a better way to handle this? */
 	init_timer();
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 	/* Find the devices we don't have hard coded knowledge about. */
 	dev_enumerate();
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 #if 0
 	x = y = 0;
-	printk_info("dump ehci3 \n");
+	printk(BIOS_INFO, "dump ehci3 \n");
 	for (; x < 16; x++) {
 		y = 0;
 		for (; y < 16; y++) {
-			printk_info("%02x ",
+			printk(BIOS_INFO, "%02x ",
 				    pci_rawread_config8(PCI_RAWDEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
-		printk_info("\n");
+		printk(BIOS_INFO, "\n");
 	}
 #endif
 
 	post_code(0x66);
 	/* Now compute and assign the bus resources. */
 	dev_configure();
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 #if 0
 	x = y = 0;
-	printk_info("dump ehci3 \n");
+	printk(BIOS_INFO, "dump ehci3 \n");
 	for (; x < 16; x++) {
 		y = 0;
 		for (; y < 16; y++) {
-			printk_info("%02x ",
+			printk(BIOS_INFO, "%02x ",
 				    pci_rawread_config8(PCI_RAWDEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
-		printk_info("\n");
+		printk(BIOS_INFO, "\n");
 	}
 #endif
 
 	post_code(0x88);
 	/* Now actually enable devices on the bus */
 	dev_enable();
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 	/* And of course initialize devices on the bus */
 #if 0
 	x = y = 0;
-	printk_info("dump ehci3 \n");
+	printk(BIOS_INFO, "dump ehci3 \n");
 	for (; x < 16; x++) {
 		y = 0;
 		for (; y < 16; y++) {
-			printk_info("%02x ",
+			printk(BIOS_INFO, "%02x ",
 				    pci_rawread_config8(PCI_RAWDEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
-		printk_info("\n");
+		printk(BIOS_INFO, "\n");
 	}
 #endif
 
 	dev_initialize();
 	post_code(0x89);
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 
 //          pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571);
 
 #if 0
 	x = y = 0;
-	printk_info("dump ehci3 \n");
+	printk(BIOS_INFO, "dump ehci3 \n");
 	for (; x < 16; x++) {
 		y = 0;
 		for (; y < 16; y++) {
-			printk_info("%02x ",
+			printk(BIOS_INFO, "%02x ",
 				    pci_rawread_config8(PCI_RAWDEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
-		printk_info("\n");
+		printk(BIOS_INFO, "\n");
 	}
 #endif
 
@@ -1265,25 +1265,25 @@
 
 #if 1
 	struct device *dev;
-	printk_info("=========zjldump all  devices...\n");
+	printk(BIOS_INFO, "=========zjldump all  devices...\n");
 	for (dev = all_devices; dev; dev = dev->next) {
 		if (dev->path.type == DEVICE_PATH_PCI) {
-			printk_debug("%s dump\n", dev_path(dev));
+			printk(BIOS_DEBUG, "%s dump\n", dev_path(dev));
 			x = y = 0;
 			for (; x < 16; x++) {
 				y = 0;
 				for (; y < 16; y++) {
-					printk_info("%02x ",
+					printk(BIOS_INFO, "%02x ",
 						    pci_read_config8(dev,
 								     x *
 								     16 +
 								     y));
 				}
-				printk_info("\n");
+				printk(BIOS_INFO, "\n");
 			}
 
 		}
-		printk_info("\n");
+		printk(BIOS_INFO, "\n");
 	}
 #endif
 
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index c1de3f3..c7efb51 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -574,7 +574,7 @@
 		__asm__ volatile ("movl   %%esp, %0\n\t":"=a" (v_esp)
 		    );
 #if CONFIG_USE_INIT
-		printk_debug("v_esp=%08x\r\n", v_esp);
+		printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
 #else
 		print_debug("v_esp=");
 		print_debug_hex32(v_esp);
@@ -590,7 +590,7 @@
 //stack
 	cpu_reset = 0;
 #if CONFIG_USE_INIT
-	printk_debug("cpu_reset = %08x\r\n", cpu_reset);
+	printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset);
 #else
 	print_debug("cpu_reset = ");
 	print_debug_hex32(cpu_reset);
@@ -642,7 +642,7 @@
 			print_debug("Use Ram as Stack now - \r\n");
 		}
 #if CONFIG_USE_INIT
-		printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
+		printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
 #else
 		print_debug("new_cpu_reset = ");
 		print_debug_hex32(new_cpu_reset);
diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c
index d1f6063..9ec54da 100644
--- a/src/northbridge/via/vx800/northbridge.c
+++ b/src/northbridge/via/vx800/northbridge.c
@@ -126,7 +126,7 @@
 	u32 pci_tolm;
 	u8 reg;
 
-	printk_spew("Entering vx800 pci_domain_set_resources.\n");
+	printk(BIOS_SPEW, "Entering vx800 pci_domain_set_resources.\n");
 
 	pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
@@ -162,7 +162,7 @@
 			    (((rambits << 6) - (4 << reg) -
 			      VIACONFIG_TOP_SM_SIZE_MB) * 1024);
 
-		printk_spew("tomk is 0x%x\n", tomk);
+		printk(BIOS_SPEW, "tomk is 0x%x\n", tomk);
 		/* Compute the Top Of Low Memory, in Kb */
 		tolmk = pci_tolm >> 10;
 		if (tolmk >= tomk) {
@@ -206,7 +206,7 @@
 
 static void enable_dev(struct device *dev)
 {
-	printk_spew("In VX800 enable_dev for device %s.\n", dev_path(dev));
+	printk(BIOS_SPEW, "In VX800 enable_dev for device %s.\n", dev_path(dev));
 
 	/* Set the operations if it is a special bus type */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c
index 732963d..58d70c3 100644
--- a/src/northbridge/via/vx800/vga.c
+++ b/src/northbridge/via/vx800/vga.c
@@ -53,7 +53,7 @@
 {
 	device_t dev;
 
-	printk_info("write_protect_vgabios\n");
+	printk(BIOS_INFO, "write_protect_vgabios\n");
 	/* there are two possible devices. Just do both. */
 	dev = dev_find_device(PCI_VENDOR_ID_VIA,
 			      PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0);
@@ -85,16 +85,16 @@
 	pci_write_config32(dev, 0x14, VIACONFIG_VGA_PCI_14);
 	pci_write_config8(dev, 0x3c, 0x0a);	//same with vx855_lpc.c
 	//*/
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 #if 1
-	printk_debug("INSTALL REAL-MODE IDT\n");
+	printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n");
 	setup_realmode_idt();
-	printk_debug("DO THE VGA BIOS\n");
+	printk(BIOS_DEBUG, "DO THE VGA BIOS\n");
 
 	do_vgabios();
 	if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) {
-		printk_debug("Enable VGA console\n");
+		printk(BIOS_DEBUG, "Enable VGA console\n");
 		// remove this function since in cn700 it is said "VGA seems to work without this, but crash & burn with it"
 		//but the existense of  vga_enable_console()  seems do not hurt my coreboot. XP+ubuntu s3 can resume with and without this function.
 		//and remove it also do not help my s3 problem: desktop screen have some thin black line, after resuming back to win.
@@ -102,7 +102,7 @@
 	}
 #else
 /* Attempt to manually force the rom to load */
-	printk_debug("Forcing rom load\r\n");
+	printk(BIOS_DEBUG, "Forcing rom load\r\n");
 	pci_rom_load(dev, 0xfff80000);
 	run_bios(dev, 0xc0000);
 #endif
@@ -122,7 +122,7 @@
 		   outb(0x39, SR_INDEX);
 		   outb(reg8, SR_DATA); */
 	}
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 }
 
diff --git a/src/northbridge/via/vx800/vgabios.c b/src/northbridge/via/vx800/vgabios.c
index b536b58..2a99b9c 100644
--- a/src/northbridge/via/vx800/vgabios.c
+++ b/src/northbridge/via/vx800/vgabios.c
@@ -302,7 +302,7 @@
 	u16 tmp;
 	u8 tmp8;
 
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 	/* clear vga bios data area */
 	for (i = 0x400; i < 0x500; i++) {
@@ -312,24 +312,24 @@
 	dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0);
 
 	if (!dev) {
-		printk_debug("NO VGA FOUND\n");
+		printk(BIOS_DEBUG, "NO VGA FOUND\n");
 		return;
 	}
-	printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
+	printk(BIOS_DEBUG, "found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
 
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
         rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom | 1);
-	printk_debug("rom base: %x\n", rom);
+	printk(BIOS_DEBUG, "rom base: %x\n", rom);
 	buf = (unsigned char *)rom;
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
 		memcpy((void *)0xc0000, buf, size);
 
-		printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+		printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 		write_protect_vgabios();	// in northbridge
 
@@ -338,14 +338,14 @@
 		if (buf[0] == 0x55 && buf[1] == 0xAA) {
 			busdevfn =
 			    (dev->bus->secondary << 8) | dev->path.pci.devfn;
-			printk_debug("bus/devfn = %#x\n", busdevfn);
+			printk(BIOS_DEBUG, "bus/devfn = %#x\n", busdevfn);
 			real_mode_switch_call_vga(busdevfn);
 		} else
-			printk_debug("Failed to copy VGA BIOS to 0xc0000\n");
+			printk(BIOS_DEBUG, "Failed to copy VGA BIOS to 0xc0000\n");
 	} else
-		printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
+		printk(BIOS_DEBUG, "BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
 
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, 0);
 }
@@ -513,12 +513,12 @@
 	cs = cs_ip >> 16;
 	flags = stackflags;
 
-	printk_debug("biosint: INT# 0x%lx\n", intnumber);
-	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
+	printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
 		     eax, ebx, ecx, edx);
-	printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
 		     ebp, esp, edi, esi);
-	printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
+	printk(BIOS_DEBUG, "biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
 		     ip, cs, flags);
 
 	// cases in a good compiler are just as good as your own tables. 
@@ -527,16 +527,16 @@
 	case 6: case 7: case 8: case 9: case 10:
 	case 11: case 12: case 13: case 14: case 15:
 		// These are not BIOS service, but the CPU-generated exceptions
-		printk_info("biosint: Oops, exception %u\n", intnumber);
+		printk(BIOS_INFO, "biosint: Oops, exception %u\n", intnumber);
 		if (esp < 0x1000) {
-			printk_debug("Stack contents: ");
+			printk(BIOS_DEBUG, "Stack contents: ");
 			while (esp < 0x1000) {
-				printk_debug("0x%04x ", *(unsigned short *)esp);
+				printk(BIOS_DEBUG, "0x%04x ", *(unsigned short *)esp);
 				esp += 2;
 			}
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
-		printk_debug("biosint: Bailing out\n");
+		printk(BIOS_DEBUG, "biosint: Bailing out\n");
 		// "longjmp"
 		if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/)	// add this to keep same with kevin's seabios patch in 2008-9-8
 			vga_exit();
@@ -556,7 +556,7 @@
 				  &ebx, &edx, &ecx, &eax, &flags);
 		break;
 	default:
-		printk_info("BIOSINT: Unsupport int #0x%x\n", intnumber);
+		printk(BIOS_INFO, "BIOSINT: Unsupport int #0x%x\n", intnumber);
 		break;
 	}
 	if (ret)
@@ -686,7 +686,7 @@
 				// devfn is an int, so we mask it off. 
 				busdevfn = (dev->bus->secondary << 8)
 				    | (dev->path.pci.devfn & 0xff);
-				printk_debug("0x%x: return 0x%x\n", func,
+				printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func,
 					     busdevfn);
 				*pebx = busdevfn;
 				retval = 0;
@@ -713,8 +713,7 @@
 			reg = *pedi;
 			dev = dev_find_slot(bus, devfn);
 			if (!dev) {
-				printk_debug
-				    ("0x%x: BAD DEVICE bus %d devfn 0x%x\n",
+				printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n",
 				     func, bus, devfn);
 				// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
 				*peax = PCIBIOS_BADREG;
@@ -749,15 +748,14 @@
 
 			if (retval)
 				retval = PCIBIOS_BADREG;
-			printk_debug
-			    ("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+			printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
 			     func, bus, devfn, reg, *pecx);
 			*peax = 0;
 			retval = 0;
 		}
 		break;
 	default:
-		printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
+		printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
 		break;
 	}
 
diff --git a/src/northbridge/via/vx800/vx800_ide.c b/src/northbridge/via/vx800/vx800_ide.c
index 673d615..b3d6bc2 100644
--- a/src/northbridge/via/vx800/vx800_ide.c
+++ b/src/northbridge/via/vx800/vx800_ide.c
@@ -169,7 +169,7 @@
 	uint8_t enables, Rx89, RxC0;
 	u8 i, data;
 	struct ATA_REG_INIT_TABLE *pEntry;
-	printk_info("ide_init\n");
+	printk(BIOS_INFO, "ide_init\n");
 
 #if 1
 	/*these 3 lines help to keep interl back door for DID VID SUBID untouched */
@@ -207,14 +207,14 @@
 	enables |= 0x02;
 	pci_write_config8(dev, IDE_CS, enables);
 	enables = pci_read_config8(dev, IDE_CS);
-	printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables);
+	printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables);
 
 	/* Enable only compatibility mode. */
 	enables = pci_read_config8(dev, IDE_CONF_II);
 	enables &= ~0xc0;
 	pci_write_config8(dev, IDE_CONF_II, enables);
 	enables = pci_read_config8(dev, IDE_CONF_II);
-	printk_debug("Enables in reg 0x42 read back as 0x%x\n", enables);
+	printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables);
 
 	/* Enable prefetch buffers. */
 	enables = pci_read_config8(dev, IDE_CONF_I);
diff --git a/src/northbridge/via/vx800/vx800_lpc.c b/src/northbridge/via/vx800/vx800_lpc.c
index 2a4550a..7a74b65 100644
--- a/src/northbridge/via/vx800/vx800_lpc.c
+++ b/src/northbridge/via/vx800/vx800_lpc.c
@@ -58,7 +58,7 @@
 
 static void pci_routing_fixup(struct device *dev)
 {
-	printk_info("%s: dev is %p\n", __FUNCTION__, dev);
+	printk(BIOS_INFO, "%s: dev is %p\n", __FUNCTION__, dev);
 
 	/* set up PCI IRQ routing */
 	pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
@@ -66,42 +66,42 @@
 	pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
 
 	/* VGA */
-	printk_info("setting vga\n");
+	printk(BIOS_INFO, "setting vga\n");
 	pci_assign_irqs(0, 0x1, pin_to_irq(vgaPins));
 
 	/* PCI slot */
-	printk_info("setting pci slot\n");
+	printk(BIOS_INFO, "setting pci slot\n");
 	pci_assign_irqs(0, 0x08, pin_to_irq(slotPins));
 
 	/* PCI slot */
-	printk_info("setting USB Device Controller\n");
+	printk(BIOS_INFO, "setting USB Device Controller\n");
 	pci_assign_irqs(0, 0x0b, pin_to_irq(usbdevicePins));
 
 	/* PCI slot */
-	printk_info("setting SDIO Controller\n");
+	printk(BIOS_INFO, "setting SDIO Controller\n");
 	pci_assign_irqs(0, 0x0c, pin_to_irq(sdioPins));
 
 	/* PCI slot */
-	printk_info("setting SD $ MS Controller\n");
+	printk(BIOS_INFO, "setting SD $ MS Controller\n");
 	pci_assign_irqs(0, 0x0d, pin_to_irq(sd_ms_ctrl_Pins));
 
 	/* PCI slot */
-	printk_info("setting CE-ATA NF Controller(Card Boot)\n");
+	printk(BIOS_INFO, "setting CE-ATA NF Controller(Card Boot)\n");
 	pci_assign_irqs(0, 0x0e, pin_to_irq(ce_ata_nf_ctrl_Pins));
 
 	/* PCI slot */
-	printk_info("setting ide\n");
+	printk(BIOS_INFO, "setting ide\n");
 	//pci_assign_irqs(0, 0x0f, pin_to_irq(idePins));
 
 	/* Standard usb components */
-	printk_info("setting usb1-2\n");
+	printk(BIOS_INFO, "setting usb1-2\n");
 //      pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
 
 	/* sound hardware */
-	printk_info("setting hdac audio\n");
+	printk(BIOS_INFO, "setting hdac audio\n");
 	pci_assign_irqs(0, 0x14, pin_to_irq(hdacaudioPins));
 
-	printk_spew("%s: DONE\n", __FUNCTION__);
+	printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__);
 }
 
 void setup_pm(device_t dev)
@@ -335,7 +335,7 @@
 
 static void southbridge_init(struct device *dev)
 {
-	printk_debug("vx800 sb init\n");
+	printk(BIOS_DEBUG, "vx800 sb init\n");
 	vx800_sb_init(dev);
 	pci_routing_fixup(dev);
 
@@ -343,8 +343,7 @@
 
 	/* turn on keyboard and RTC, no need to visit this reg twice */
 	pc_keyboard_init(0);
-	printk_debug
-	    ("ps2 usb lid, you  set who can wakeup system from s3 sleep\n");
+	printk(BIOS_DEBUG, "ps2 usb lid, you  set who can wakeup system from s3 sleep\n");
 	S3_ps2_kb_ms_wakeup(dev);
 	S3_usb_wakeup(dev);