chip soc/intel/alderlake

	device cpu_cluster 0 on
		device lapic 0 on end
	end

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "pmc_gpe0_dw0" = "GPP_B"
	register "pmc_gpe0_dw1" = "GPP_D"
	register "pmc_gpe0_dw2" = "GPP_E"

	# Enable HECI1 interface
	register "HeciEnabled" = "1"

	# FSP configuration

	# Enable CNVi BT
	register "CnviBtCore" = "true"

	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1
	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-C Port2
	register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"		# Type-C Port3
	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"		# Type-C Port4
	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# FPS connector
	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"		# USB3/2 Type A port1
	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"		# USB3/2 Type A port2
	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"		# USB3/2 Type A port3
	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WLAN

	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type A port1
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port2
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port3
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN

	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
	register "gen1_dec" = "0x00fc0801"
	register "gen2_dec" = "0x000c0201"
	# EC memory map range is 0x900-0x9ff
	register "gen3_dec" = "0x00fc0901"

	# This disabled autonomous GPIO power management, otherwise
	# old cr50 FW only supports short pulses; need to clarify
	# the minimum PCH IRQ pulse width with Intel, b/180111628
	register "gpio_override_pm" = "1"
	register "gpio_pm[COMM_0]" = "0"
	register "gpio_pm[COMM_1]" = "0"
	register "gpio_pm[COMM_2]" = "0"
	register "gpio_pm[COMM_4]" = "0"
	register "gpio_pm[COMM_5]" = "0"

	# Enable PCH PCIE RP 5 using CLK 2
	register "pch_pcie_rp[PCH_RP(5)]" = "{
		.clk_src = 2,
		.clk_req = 2,
		.flags = PCIE_RP_CLK_REQ_DETECT,
	}"

	# Enable PCH PCIE RP 6 using CLK 5
	register "pch_pcie_rp[PCH_RP(6)]" = "{
		.clk_src = 5,
		.clk_req = 5,
		.flags = PCIE_RP_CLK_REQ_DETECT,
	}"

	# Enable PCH PCIE RP 8 using free running CLK (0x80)
	# Clock source is shared with LAN and hence marked as free running.
	register "pch_pcie_rp[PCH_RP(8)]" = "{
		.flags = PCIE_RP_CLK_SRC_UNUSED,
	}"
	register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"

	# Enable PCH PCIE RP 9 using CLK 1
	register "pch_pcie_rp[PCH_RP(9)]" = "{
		.clk_src = 1,
		.clk_req = 1,
		.flags = PCIE_RP_CLK_REQ_DETECT,
	}"

	# Enable PCH PCIE RP 11 for optane
	register "pch_pcie_rp[PCH_RP(11)]" = "{
		.flags = PCIE_RP_CLK_SRC_UNUSED,
	}"

	# Hybrid storage mode
	register "HybridStorageMode" = "1"

	# Enable CPU PCIE RP 1 using CLK 0
	register "cpu_pcie_rp[CPU_RP(1)]" = "{
		.clk_req = 0,
		.clk_src = 0,
	}"

	# Enable CPU PCIE RP 2 using CLK 3
	register "cpu_pcie_rp[CPU_RP(2)]" = "{
		.clk_req = 3,
		.clk_src = 3,
        }"

	# Enable CPU PCIE RP 3 using CLK 4
	register "cpu_pcie_rp[CPU_RP(3)]" = "{
		.clk_req = 4,
		.clk_src = 4,
	}"

	register "SataSalpSupport" = "1"

	register "SataPortsEnable" = "{
		[0] = 1,
		[1] = 1,
		[2] = 1,
		[3] = 1,
	}"

	register "SataPortsDevSlp" = "{
		[0] = 1,
		[1] = 1,
		[2] = 1,
		[3] = 1,
	}"

	# Enable EDP in PortA
	register "DdiPortAConfig" = "1"
	# Enable HDMI in Port B
	register "DdiPortBDdc" = "1"
	register "DdiPortBHpd" = "1"

	# TCSS USB3
	register "TcssAuxOri" = "0"

	register "s0ix_enable" = "1"
	register "dptf_enable" = "1"

	register "power_limits_config" = "{
		.tdp_pl1_override = 45,
		.tdp_pl2_override = 56,
	}"

	register "SerialIoI2cMode" = "{
		[PchSerialIoIndexI2C0] = PchSerialIoPci,
		[PchSerialIoIndexI2C1] = PchSerialIoPci,
		[PchSerialIoIndexI2C2] = PchSerialIoPci,
		[PchSerialIoIndexI2C3] = PchSerialIoPci,
		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
		[PchSerialIoIndexI2C5] = PchSerialIoPci,
	}"

	register "SerialIoGSpiMode" = "{
		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
	}"

	register "SerialIoGSpiCsMode" = "{
		[PchSerialIoIndexGSPI0] = 0,
		[PchSerialIoIndexGSPI1] = 0,
		[PchSerialIoIndexGSPI2] = 0,
		[PchSerialIoIndexGSPI3] = 0,
	}"

	register "SerialIoGSpiCsState" = "{
		[PchSerialIoIndexGSPI0] = 0,
		[PchSerialIoIndexGSPI1] = 0,
		[PchSerialIoIndexGSPI2] = 0,
		[PchSerialIoIndexGSPI3] = 0,
	}"

	register "SerialIoUartMode" = "{
		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
	}"

	# HD Audio
	register "PchHdaDspEnable" = "1"
	register "PchHdaIDispLinkTmode" = "HDA_TMODE_4T"
	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
	register "PchHdaIDispCodecEnable" = "1"

	register "CnviBtAudioOffload" = "true"

	# Intel Common SoC Config
	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
		.i2c[0] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[1] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[2] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[3] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[5] = {
			.speed = I2C_SPEED_FAST,
		},
	}"

	device domain 0 on
		device pci 00.0 on  end # Host Bridge
		device pci 01.0 on  end # PEG10
		device pci 02.0 on  end # Graphics
		device pci 04.0 on
			chip drivers/intel/dptf

				## sensor information
				register "options.tsr[0].desc" = ""Ambient""
				register "options.tsr[1].desc" = ""Battery""
				register "options.tsr[2].desc" = ""DDR""
				register "options.tsr[3].desc" = ""Skin""

				## Active Policy
				# TODO: below values are initial reference values only
				register "policies.active" = "{
					[0] = {
							.target = DPTF_CPU,
							.thresholds = {
								TEMP_PCT(95, 90),
								TEMP_PCT(90, 80),
							}
						},
					[1] = {
							.target = DPTF_TEMP_SENSOR_0,
							.thresholds = {
								TEMP_PCT(80, 90),
								TEMP_PCT(70, 80),
							}
						}
				}"

				## Passive Policy
				# TODO: below values are initial reference values only
				register "policies.passive" = "{
					[0] = DPTF_PASSIVE(CPU,		CPU,	       95, 10000),
					[1] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_0, 85, 50000),
					[2] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_1, 85, 50000),
					[3] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_2, 85, 50000),
					[4] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_3, 85, 50000),
				}"

				## Critical Policy
				# TODO: below values are initial reference values only
				register "policies.critical" = "{
					[0] = DPTF_CRITICAL(CPU,	  105, SHUTDOWN),
					[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
					[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
					[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
					[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN),
				}"

				## Power Limits Control
				register "controls.power_limits" = "{
					.pl1 = {
							.min_power = 35000,
							.max_power = 45000,
							.time_window_min = 28 * MSECS_PER_SEC,
							.time_window_max = 32 * MSECS_PER_SEC,
							.granularity = 200,
					},
					.pl2 = {
							.min_power = 56000,
							.max_power = 56000,
							.time_window_min = 28 * MSECS_PER_SEC,
							.time_window_max = 32 * MSECS_PER_SEC,
							.granularity = 1000,
					}
				}"

				## Charger Performance Control (Control, mA)
				register "controls.charger_perf" = "{
					[0] = { 255, 3000 },
					[1] = {  24, 1500 },
					[2] = {  16, 1000 },
					[3] = {   8,  500 }
				}"

				## Fan Performance Control (Percent, Speed, Noise, Power)
				register "controls.fan_perf" = "{
					[0] = {  90, 6700, 220, 2200, },
					[1] = {  80, 5800, 180, 1800, },
					[2] = {  70, 5000, 145, 1450, },
					[3] = {  60, 4900, 115, 1150, },
					[4] = {  50, 3838,  90,  900, },
					[5] = {  40, 2904,  55,  550, },
					[6] = {  30, 2337,  30,  300, },
					[7] = {  20, 1608,  15,  150, },
					[8] = {  10,  800,  10,  100, },
					[9] = {   0,    0,   0,   50, }
				}"

				## Fan options
				register "options.fan.fine_grained_control" = "1"
				register "options.fan.step_size" = "2"

				device generic 0 on end
			end
		end # DPTF
		device pci 05.0 on  end # IPU
		device pci 06.0 on  end # PEG60
		device pci 06.2 on  end # PEG62
		device pci 07.0 on  end # TBT_PCIe0
		device pci 07.1 on  end # TBT_PCIe1
		device pci 07.2 on  end # TBT_PCIe2
		device pci 07.3 on  end # TBT_PCIe3
		device pci 08.0 off end # GNA
		device pci 09.0 off end # NPK
		device pci 0a.0 off end # Crash-log SRAM
		device pci 0d.0 on  end # USB xHCI
		device pci 0d.1 on  end # USB xDCI (OTG)
		device pci 0d.2 on  end # TBT DMA0
		device pci 0d.3 on  end # TBT DMA1
		device pci 0e.0 off end # VMD
		device pci 10.0 off end
		device pci 10.1 off end
		device pci 12.0 off end # SensorHUB
		device pci 12.6 off end # GSPI2
		device pci 13.0 off end # GSPI3
		device pci 14.0 on
			chip drivers/usb/acpi
				register "desc" = ""Root Hub""
				register "type" = "UPC_TYPE_HUB"
				device usb 0.0 on
					chip drivers/usb/acpi
						register "desc" = ""Bluetooth""
						register "type" = "UPC_TYPE_INTERNAL"
						device usb 2.9 on end
					end
				end
			end
		end # USB3.1 xHCI
		device pci 14.1 off end # USB3.1 xDCI
		device pci 14.2 off end # Shared RAM
		device pci 14.3 on
			chip drivers/wifi/generic
				register "wake" = "GPE0_PME_B0"
				device generic 0 on end
			end
		end # CNVi: WiFi
		device pci 15.0 on  end # I2C0
		device pci 15.1 on  end # I2C1
		device pci 15.2 on  end # I2C2
		device pci 15.3 on  end # I2C3
		device pci 16.0 on  end # HECI1
		device pci 16.1 off end # HECI2
		device pci 16.2 off end # CSME
		device pci 16.3 off end # CSME
		device pci 16.4 off end # HECI3
		device pci 16.5 off end # HECI4
		device pci 17.0 on  end # SATA
		device pci 19.0 off end # I2C4
		device pci 19.1 on  end # I2C5
		device pci 19.2 off end # UART2
		device pci 1c.0 on  end # RP1
		device pci 1c.1 off end # RP2
		device pci 1c.2 on  end # RP3 # W/A to FSP issue
		device pci 1c.3 on  end # RP4 # W/A to FSP issue
		device pci 1c.4 on  end # RP5
		device pci 1c.5 on  end # RP6
		device pci 1c.6 off end # RP7
		device pci 1c.7 on  end # RP8
		device pci 1d.0 on  end # RP9
		device pci 1d.1 off end # RP10
		device pci 1d.2 on  end # RP11
		device pci 1d.3 off end # RP12
		device pci 1e.0 on  end # UART0
		device pci 1e.1 off end # UART1
		device pci 1e.2 on  end # GSPI0
		device pci 1e.3 off end # GSPI1
		device pci 1f.0 on  end # eSPI
		device pci 1f.1 on  end # P2SB
		device pci 1f.2 hidden  end # PMC
		device pci 1f.3 on
			chip drivers/intel/soundwire
				device generic 0 on
					chip drivers/soundwire/alc711
						# SoundWire Link 0 ID 1
						register "desc" = ""Headset Codec""
						device generic 0.1 on end
					end
				end
			end
		end # Intel Audio SNDW
		device pci 1f.4 on  end # SMBus
		device pci 1f.5 on  end # SPI
		device pci 1f.6 off end # GbE
		device pci 1f.7 off end # TH
	end
end