Documentation/Intel: Add minimal APCI and TempRamExit documentation
Update the documentation to add the minimal ACPI support. Also add
TempRamExit entry to the FSP features table.
TEST=None
Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13757
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html
index 91aa305..e157780 100644
--- a/Documentation/Intel/Board/board.html
+++ b/Documentation/Intel/Board/board.html
@@ -17,6 +17,7 @@
<li>Enable <a href="#SerialOutput">Serial Output</a></li>
<li>Load the <a href="#SpdData">Memory Timing Data</a></li>
<li><a href="#DisablePciDevices">Disable</a> the PCI devices</li>
+ <li><a href="#AcpiTables">ACPI Tables</a></li>
</ol>
@@ -208,7 +209,33 @@
</ol>
+
<hr>
-<p>Modified: 15 February 2016</p>
+<h1><a name="AcpiTables">ACPI Tables</a></h1>
+<ol>
+ <li>Edit Kconfig
+ <ol type="A">
+ <li>Add "select HAVE_ACPI_TABLES"</li>
+ </ol>
+ </li>
+ <li>Add the acpi_tables.c module:
+ <ol type="A">
+ <li>Include soc/acpi.h</li>
+ <li>Add the acpi_create_fadt routine
+ <ol type="I">
+ <li>fill in the ACPI header</li>
+ <li>Call the acpi_fill_in_fadt routine</li>
+ </ol>
+ </li>
+ </ol>
+ </li>
+ <li>Add the dsdt.asl module:
+ </li>
+</ol>
+
+
+
+<hr>
+<p>Modified: 20 February 2016</p>
</body>
</html>
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diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index 146e768..3e72da3 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -32,6 +32,7 @@
<li>Set up the <a href="#MemoryMap">Memory Map"</a></li>
</ol>
</li>
+ <li><a href="#AcpiTables">ACPI Tables</a></li>
</ol>
@@ -556,8 +557,52 @@
+<hr>
+<h1><a name="AcpiTables">ACPI Tables</a></h1>
+<p>
+ One of the payloads that needs ACPI tables is the EDK2 CorebootPayloadPkg.
+</p>
+
+<h2>FADT</h2>
+<p>
+ The EDK2 module
+ CorebootModulePkg/CbSupportPei/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPei/CbSupportPei.c#l342">CbSupportPei.c</a>
+ requires that the FADT contains the following values:
+</p>
+<table border="1">
+ <tr bgcolor="#c0ffc0">
+ <td>EDK2 Field</td>
+ <td>Coreboot Field</td>
+ </tr>
+ <tr><td>Pm1aCntBlk</td><td>pm1a_cnt_blk</td></tr>
+ <tr><td>PmTmrBlk</td><td>pm_tmr_blk</td></tr>
+ <tr><td>ResetReg.Address</td><td>reset_reg.</td></tr>
+ <tr><td>ResetValue</td><td>reset_value</td></tr>
+ <tr><td>Pm1aEvtBlk</td><td>pm1a_evt_blk</td></tr>
+ <tr><td>Gpe0Blk</td><td>gpe0_blk</td></tr>
+ <tr><td>Gpe0BlkLen</td><td>gpe0_blk_len</td></tr>
+</table>
+<p>
+ The EDK2 data structure is defined in
+ MdeModulePkg/Include/IndustryStandard/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/MdePkg/Include/IndustryStandard/Acpi61.h#l111">Acpi61.h</a>
+ The coreboot data structure is defined in
+ src/arch/x86/include/arch/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/acpi.h;hb=HEAD#l237">acpi.h</a>
+</p>
+
+<ol>
+ <li>
+ Select <a target="_blank" href="../Board/board.html#AcpiTables">HAVE_ACPI_TABLES</a>
+ in the board's Kconfig file
+ </li>
+ <li>Create a acpi.c module:
+ <ol type="A">
+ <li>Add the acpi_fill_in_fadt routine and initialize the values above</li>
+ </ol>
+ </li>
+</ol>
+
<hr>
-<p>Modified: 18 February 2016</p>
+<p>Modified: 20 February 2016</p>
</body>
</html>
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diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html
index a3136d1..74a476f 100644
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@@ -116,6 +116,21 @@
+<h2>Add coreboot Features</h2>
+<p>
+ Most of the coreboot development gets done in this phase. Implementation tasks in this
+ phase are easily done in parallel.
+</p>
+<ul>
+ <li>Payload and OS Features:
+ <ul>
+ <li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li>
+ </ul>
+ </li>
+</ul>
+
+
+
<hr>
<table border="1">
<tr bgcolor="#c0ffc0">
@@ -229,6 +244,20 @@
<tr bgcolor="#c0ffc0">
+ <th>Payload</th>
+ <th>Where</th>
+ <th>Testing</th>
+ </tr>
+ <tr>
+ <td>ACPI Tables</td>
+ <td>
+ SoC <a target="_blank" href="SoC/soc.html#AcpiTables">Support</a><br>
+ </td>
+ <td>Verified by payload or OS</td>
+ </tr>
+
+
+ <tr bgcolor="#c0ffc0">
<th>FSP</th>
<th>Where</th>
<th>Testing</th>
@@ -265,6 +294,18 @@
</td>
</tr>
<tr>
+ <td>TempRamExit</td>
+ <td>src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td>
+ <td>Post code 0x91
+ (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l212">POST_FSP_TEMP_RAM_EXIT</a>)
+ is displayed before calling TempRamExit by
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a>,
+ CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and
+ Post code 0x39 is displayed by
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a><br>
+ </td>
+ </tr>
+ <tr>
<td>SiliconInit</td>
<td>
Implement the .init routine for the
@@ -294,6 +335,6 @@
<hr>
-<p>Modified: 15 February 2016</p>
+<p>Modified: 20 February 2016</p>
</body>
</html>
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