soc/intel/tigerlake: update elog to include CSME reset causes
Call out the CSME-initiated bits from HPR_CAUSE0 register and
update the elog to include reset causes
Change-Id: I32ffb55ff2ad26ec4e7609c41fc65e021a327a14
Signed-off-by: derek.huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c
index 586dbfd..d5b8754 100644
--- a/src/soc/intel/tigerlake/elog.c
+++ b/src/soc/intel/tigerlake/elog.c
@@ -61,6 +61,18 @@
if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
elog_add_event(ELOG_TYPE_THERM_TRIP);
+ /* CSME-Initiated Host Reset with power down */
+ if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPD)
+ elog_add_event(ELOG_TYPE_MI_HRPD);
+
+ /* CSME-Initiated Host Reset with power cycle */
+ if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPC)
+ elog_add_event(ELOG_TYPE_MI_HRPC);
+
+ /* CSME-Initiated Host Reset without power cycle */
+ if (ps->hpr_cause0 & HPR_CAUSE0_MI_HR)
+ elog_add_event(ELOG_TYPE_MI_HR);
+
/* PWR_FLR Power Failure */
if (ps->gen_pmcon_a & PWR_FLR)
elog_add_event(ELOG_TYPE_POWER_FAIL);