x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 0b2acd7..776c051 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -156,7 +156,7 @@
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
- pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
@@ -177,8 +177,8 @@
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
/* Hardware default is 8MB UMA. If someone wants to make this a
@@ -342,7 +342,7 @@
RCBA32(ULD) |= (1 << 24) | (1 << 16);
- RCBA32(ULBA) = DEFAULT_DMIBAR;
+ RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR;
RCBA32(RP1D) |= (2 << 16);
RCBA32(RP2D) |= (2 << 16);
@@ -818,7 +818,7 @@
EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0);
- EPBAR32(EPLE1A) = DEFAULT_DMIBAR;
+ EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR;
EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0);
@@ -833,7 +833,7 @@
reg32 |= (1 << 0);
DMIBAR32(DMILE1D) = reg32;
- DMIBAR32(DMILE1A) = DEFAULT_RCBA;
+ DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA;
DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0);
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index fe59ebe..7d02b37 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -23,8 +23,13 @@
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_X60BAR 0xfed13000
+#ifndef __ACPI__
+#define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
+#else
#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 0a60112..c3f9bae 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -90,7 +90,7 @@
{
PRINTK_DEBUG(" ram read: %08x\n", offset);
- read32(offset);
+ read32((void *)offset);
}
#if CONFIG_DEBUG_RAM_SETUP
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index 88d6a00..6d429e4 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -42,8 +42,8 @@
}
for (i = 0; i < 28; i++) {
- read32(addr);
- read32(addr + 0x80);
+ read32((void *)addr);
+ read32((void *)(addr + 0x80));
}
reg32 = MCHBAR32(RCVENMT);