nvs: Add Chrome OS NVS (CNVS) information to coreboot tables
CB:51638 separated Chrome OS NVS from global NVS by allocating it
separately in CBMEM. CNVS is used in depthcharge to fill firmware
information at boot time. Thus, location of CNVS needs to be shared in
coreboot tables for depthcharge to use.
This change adds a new coreboot table tag
`CB_TAG_ACPI_CNVS`/`CB_TAG_ACPI_CNVS`(0x41) which provides the
location of CNVS in CBMEM to payload (depthcharge).
Additionally, CB:51639 refactored device nvs(DNVS) and moved it to the
end of GNVS instead of the fixed offset 0x1000. DNVS is used on older
Intel platforms like baytrail, braswell and broadwell and depthcharge
fills this at boot time as well. Since DNVS is no longer used on any
new platforms, this information is not passed in coreboot
tables. Instead depthcharge is being updated to use statically defined
offsets for DNVS.
BUG=b:191324611, b:191324611
TEST=Verified that `crossystem fwid` which reads fwid information from
CNVS is reported correctly on brya.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3815d5ecb5f0b534ead61836c2d275083e397ff0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55665
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index e042a90..91f8486 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -81,6 +81,7 @@
CB_TAG_FMAP = 0x0037,
CB_TAG_SMMSTOREV2 = 0x0039,
CB_TAG_BOARD_CONFIG = 0x0040,
+ CB_TAG_ACPI_CNVS = 0x0041,
CB_TAG_CMOS_OPTION_TABLE = 0x00c8,
CB_TAG_OPTION = 0x00c9,
CB_TAG_OPTION_ENUM = 0x00ca,
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index 5a24e14..26dece7 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -109,6 +109,7 @@
uintptr_t cbmem_cons;
uintptr_t mrc_cache;
uintptr_t acpi_gnvs;
+ uintptr_t acpi_cnvs;
#define UNDEFINED_STRAPPING_ID (~0)
#define UNDEFINED_FW_CONFIG ~((uint64_t)0)
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 7e23afe..269275d 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -143,6 +143,11 @@
info->acpi_gnvs = get_cbmem_addr(ptr);
}
+static void cb_parse_acpi_cnvs(unsigned char *ptr, struct sysinfo_t *info)
+{
+ info->acpi_cnvs = get_cbmem_addr(ptr);
+}
+
static void cb_parse_board_config(unsigned char *ptr, struct sysinfo_t *info)
{
struct cb_board_config *const config = (struct cb_board_config *)ptr;
@@ -380,6 +385,9 @@
case CB_TAG_ACPI_GNVS:
cb_parse_acpi_gnvs(ptr, info);
break;
+ case CB_TAG_ACPI_CNVS:
+ cb_parse_acpi_cnvs(ptr, info);
+ break;
case CB_TAG_BOARD_CONFIG:
cb_parse_board_config(ptr, info);
break;
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index be40c38..fd7461d5 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -83,6 +83,7 @@
LB_TAG_SMMSTOREV2 = 0x0039,
LB_TAG_TPM_PPI_HANDOFF = 0x003a,
LB_TAG_BOARD_CONFIG = 0x0040,
+ LB_TAG_ACPI_CNVS = 0x0041,
/* The following options are CMOS-related */
LB_TAG_CMOS_OPTION_TABLE = 0x00c8,
LB_TAG_OPTION = 0x00c9,
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 9264efb..27f5315 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -246,6 +246,7 @@
{CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS},
{CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE},
{CBMEM_ID_ACPI_GNVS, LB_TAG_ACPI_GNVS},
+ {CBMEM_ID_ACPI_CNVS, LB_TAG_ACPI_CNVS},
{CBMEM_ID_VPD, LB_TAG_VPD},
{CBMEM_ID_WIFI_CALIBRATION, LB_TAG_WIFI_CALIBRATION},
{CBMEM_ID_TCPA_LOG, LB_TAG_TCPA_LOG},