coreboot: common stage cache
Many chipsets were using a stage cache for reference code
or when using a relocatable ramstage. Provide a common
API for the chipsets to use while reducing code duplication.
Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
diff --git a/src/include/program_loading.h b/src/include/program_loading.h
index 2699887..02e6f5f 100644
--- a/src/include/program_loading.h
+++ b/src/include/program_loading.h
@@ -123,18 +123,8 @@
/* Run ramstage from romstage. */
void run_ramstage(void);
-struct romstage_handoff;
-#if IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)
-/* Cache the loaded ramstage described by prog. */
-void cache_loaded_ramstage(struct romstage_handoff *, struct prog *p);
-/* Load ramstage from cache filling in struct prog. */
-void load_cached_ramstage(struct romstage_handoff *h, struct prog *p);
-#else
-static inline void cache_loaded_ramstage(struct romstage_handoff *h,
- struct prog *p) {}
-static inline void load_cached_ramstage(struct romstage_handoff *h,
- struct prog *p) {}
-#endif
+/* Called when the stage cache couldn't load ramstage on resume. */
+void ramstage_cache_invalid(void);
/***********************
* PAYLOAD LOADING *