mb/roda/rv11: Add new boards Lizard RV11 and RW11
The Roda Lizard RV11 is a comparatively lightweight, full-rugged
notebook. It's based on a 17W TDP dual core Ivy Bridge CPU.
The Lizard RW11 is its bigger brother (45W TDP quad core, more i/o
options).
The RV11 is the first board to use the native graphics initialization
by libgfxinit. Tested so far, are the internal eDP port, DP and VGA.
Change-Id: Iea283059ce3402dc36184baf16928b55285a9eeb
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17446
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
new file mode 100644
index 0000000..845bca8
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
@@ -0,0 +1,178 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 secunet Security Networks AG
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "4"
+ register "gfx.did" = "{ 0x80000400, 0x80000300, 0x80000301, 0x80000100, }"
+
+ # Enable Panel as eDP and configure power delays
+ register "gpu_panel_port_select" = "1" # eDP_A
+ register "gpu_panel_power_cycle_delay" = "6" # 500ms
+ register "gpu_panel_power_up_delay" = "2000" # 200ms
+ register "gpu_panel_power_down_delay" = "500" # 50ms
+ register "gpu_panel_power_backlight_on_delay" = "1" # 100us as recommended by PRM
+ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
+
+ # Set backlight PWM values for eDP
+ register "gpu_cpu_backlight" = "0x00000ac8"
+ register "gpu_pch_backlight" = "0x13120000"
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6)
+ register "c3_acpower" = "0"
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6)
+ register "c3_battery" = "0"
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ # LPC i/o generic decodes
+ register "gen1_dec" = "0x003c0a01" # ITE environment controller
+ register "gen2_dec" = "0x000403e9" # additional com port
+ register "gen3_dec" = "0x000402e9" # additional com port
+
+ # Enable both SATA ports 0, 1
+ register "sata_port_map" = "0x03"
+ # Set max SATA speed to 6.0 Gb/s (should be the default, anyway)
+ register "sata_interface_speed_support" = "0x3"
+
+ # Route GPI7 (EC SCI) as SCI
+ register "gpi7_routing" = "2"
+
+ # Enable GPE17 (GPI7) and TCO SCI
+ register "gpe0_en" = "0x00800040"
+
+ # Disable root port coalescing
+ register "pcie_port_coalesce" = "0"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }"
+
+ register "p_cnt_throttling_supported" = "1"
+
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0f"
+ register "superspeed_capable_ports" = "0x0f"
+
+ register "spi_uvscc" = "0x2005"
+ register "spi_lvscc" = "0x2005"
+
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on # High Definition Audio
+ subsystemid 0x1a86 0x4352
+ end
+
+ # Disabling 1c.0 might break IRQ settings as it enables port coalescing
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2
+ device pci 1c.2 on end # PCIe Port #3
+ device pci 1c.3 on end # PCIe Port #4
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1c.5 on end # PCIe Port #6
+ device pci 1c.6 on end # PCIe Port #7
+ device pci 1c.7 on end # PCIe Port #8
+
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip ec/roda/it8518
+ register "cpuhot_limit" = "100"
+ # 60h/64h KBC
+ device pnp ff.0 on # dummy address
+ end
+ end
+ chip superio/ite/it8783ef
+ register "TMPIN1" = "THERMAL_RESISTOR"
+ register "TMPIN2" = "THERMAL_RESISTOR"
+ register "ec.vin_mask" = "VIN_ALL"
+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
+ register "FAN1.smart.tmpin" = " 1"
+ register "FAN1.smart.tmp_off" = "60"
+ register "FAN1.smart.tmp_start" = "64"
+ register "FAN1.smart.tmp_delta" = " 2"
+ register "FAN1.smart.pwm_start" = "30"
+ register "FAN1.smart.slope" = "64"
+ register "FAN2.mode" = "FAN_SMART_AUTOMATIC"
+ register "FAN2.smart.tmpin" = " 1"
+ register "FAN2.smart.tmp_off" = "60"
+ register "FAN2.smart.tmp_start" = "64"
+ register "FAN2.smart.tmp_delta" = " 2"
+ register "FAN2.smart.pwm_start" = "30"
+ register "FAN2.smart.slope" = "64"
+ register "FAN3.mode" = "FAN_MODE_OFF"
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 on # COM 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 on # COM 2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Printer Port
+ io 0x60 = 0x378
+ io 0x62 = 0x000
+ irq 0x70 = 7
+ drq 0x74 = 4
+ irq 0xf0 = 0x00
+ end
+ device pnp 2e.4 on # Environment Controller
+ io 0x60 = 0xa30
+ io 0x62 = 0xa20
+ irq 0x70 = 0
+ irq 0xf0 = 0x80
+ end
+ device pnp 2e.5 off end # Keyboard
+ device pnp 2e.6 off end # Mouse
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.8 on # COM 3
+ io 0x60 = 0x3e8
+ irq 0x70 = 4
+ end
+ device pnp 2e.9 on # COM 4
+ io 0x60 = 0x2e8
+ irq 0x70 = 3
+ end
+ device pnp 2e.a off end # COM 5
+ device pnp 2e.b off end # COM 6
+ device pnp 2e.c off end # CIR
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads b/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads
new file mode 100644
index 0000000..52b81fa
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads
@@ -0,0 +1,20 @@
+with HW.GFX.GMA;
+
+use HW.GFX.GMA;
+
+private package GMA.Mainboard is
+
+ -- For a three-pipe setup, bandwidth is shared between the 2nd and
+ -- the 3rd pipe (if it's not eDP). Thus, probe ports that likely
+ -- have a high-resolution display attached first, `Internal` last.
+
+ ports : constant Port_List :=
+ (DP2,
+ DP3,
+ Digital2,
+ Digital3,
+ Analog,
+ Internal,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl b/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl
new file mode 100644
index 0000000..7dba1f2
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl
@@ -0,0 +1,19 @@
+Scope (GFX0)
+{
+ Name (BRIG, Package (13)
+ {
+ 74, /* default AC */
+ 74, /* default Battery */
+ 9, /* 439 / 4882 */
+ 11, /* 537 / 4882 */
+ 14, /* 683 / 4882 */
+ 18, /* 878 / 4882 */
+ 22, /* 1074 / 4882 */
+ 28, /* 1366 / 4882 */
+ 36, /* 1757 / 4882 */
+ 46, /* 2245 / 4882 */
+ 58, /* 2831 / 4882 */
+ 74, /* 3612 / 4882 */
+ 100, /* 4882 / 4882 */
+ })
+}
diff --git a/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl b/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl
new file mode 100644
index 0000000..ae53167
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#undef IT8783EF_SHOW_UARTA
+#undef IT8783EF_SHOW_UARTB
+#undef IT8783EF_SHOW_UARTC
+#undef IT8783EF_SHOW_UARTD
+#undef IT8783EF_SHOW_KBC
+#undef IT8783EF_SHOW_PS2M
+#define SUPERIO_DEV SIO0
+#define SUPERIO_PNP_BASE 0x2e
+#define IT8783EF_SHOW_UARTA 1
+#define IT8783EF_SHOW_UARTB 1
+#define IT8783EF_SHOW_UARTC 1
+#define IT8783EF_SHOW_UARTD 1
+#include <superio/ite/it8783ef/acpi/superio.asl>
diff --git a/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h
new file mode 100644
index 0000000..edc5f64
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0262, /* Codec Vendor / Device ID: Realtek ALC262 */
+ 0x1a864352, /* Subsystem ID */
+ 0x0000000e, /* Number of jacks */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0262 */
+ AZALIA_SUBVENDOR(0, 0x1a864352),
+
+ AZALIA_PIN_CFG(0, 0x11, 0x18561180),
+
+ AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+
+ AZALIA_PIN_CFG(0, 0x15, 0x03214020),
+
+ AZALIA_PIN_CFG(0, 0x16, 0x40000000),
+
+ AZALIA_PIN_CFG(0, 0x18, 0x03a19040),
+
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x1a, 0x03813050),
+
+ AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x1d, 0x40d6862d),
+
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+ /* coreboot specific header */
+ 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */
+ 0x80860101, /* Subsystem ID */
+ 0x00000004, /* Number of jacks */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
diff --git a/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h b/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h
new file mode 100644
index 0000000..d3b72cd
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define CRITICAL_TEMPERATURE 100
+#define PASSIVE_TEMPERATURE 95
diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/romstage.c
new file mode 100644
index 0000000..ca705a4
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/romstage.c
@@ -0,0 +1,145 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <device/pci.h>
+#include <device/pnp.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/ite/it8783ef/it8783ef.h>
+#include <superio/ite/common/ite.h>
+
+void pch_enable_lpc(void)
+{
+ /* COMA on 0x3f8, COMB on 0x2f8 */
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
+ /* Enable KBC on 0x60/0x64 (KBC),
+ EC on 0x62/0x66 (MC),
+ SIO on 0x2e/0x2f (CNF1) */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
+ COMB_LPC_EN | COMA_LPC_EN);
+}
+
+void mainboard_config_superio(void)
+{
+ const pnp_devfn_t dev = PNP_DEV(0x2e, IT8783EF_GPIO);
+
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+
+ pnp_write_config(dev, 0x23, ITE_UART_CLK_PREDIVIDE_24);
+
+ /* Switch multi function for UART4 */
+ pnp_write_config(dev, 0x2a, 0x04);
+ /* Switch multi function for UART3 */
+ pnp_write_config(dev, 0x2c, 0x13);
+
+ /* No GPIOs used: Clear any output / pull-up that's set by default */
+ pnp_write_config(dev, 0xb8, 0x00);
+ pnp_write_config(dev, 0xc0, 0x00);
+ pnp_write_config(dev, 0xc3, 0x00);
+ pnp_write_config(dev, 0xc8, 0x00);
+ pnp_write_config(dev, 0xcb, 0x00);
+ pnp_write_config(dev, 0xef, 0x00);
+
+ pnp_exit_conf_state(dev);
+}
+
+void mainboard_fill_pei_data(struct pei_data *const pei_data)
+{
+ const struct pei_data pei_data_template = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 0, // 0 Mobile, 1 Desktop/Server
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 },
+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+ .ec_present = 1,
+ .gbe_enable = 1,
+ .ddr3lv_support = 0,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ .dimm_channel0_disabled = 0,
+ .dimm_channel1_disabled = 0,
+ .max_ddr3_freq = 1600,
+ .usb_port_config = {
+ /* Enabled / OC PIN / Length */
+ { 1, 0, 0x0080 }, /* P00: 1st (left) USB3 (OC #0) */
+ { 1, 0, 0x0080 }, /* P01: 2nd (left) USB3 (OC #0) */
+ { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */
+ { 1, 1, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #1) */
+ { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */
+ { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */
+ { 1, 8, 0x0040 }, /* P06: USB Hub x4 USB2 (no OC) */
+ { 1, 8, 0x0040 }, /* P07: MiniPCIe 4 USB2 (no OC) */
+ { 1, 8, 0x0080 }, /* P08: SD card reader USB2 (no OC) */
+ { 1, 4, 0x0080 }, /* P09: 3rd (right) USB2 (OC #4) */
+ { 1, 5, 0x0040 }, /* P10: 4th (right) USB2 (OC #5) */
+ { 1, 8, 0x0040 }, /* P11: 3rd Multibay USB2 (no OC) */
+ { 1, 8, 0x0080 }, /* P12: misc internal USB2 (no OC) */
+ { 1, 6, 0x0080 }, /* P13: misc internal USB2 (OC #6) */
+ },
+ .usb3 = {
+ .mode = 3, /* Smart Auto? */
+ .hs_port_switch_mask = 0xf, /* All four ports. */
+ .preboot_support = 1, /* preOS driver? */
+ .xhci_streams = 1, /* Enable. */
+ },
+ .pcie_init = 1,
+ };
+ *pei_data = pei_data_template;
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ /* Enabled / Power / OC PIN */
+ { 1, 1, 0 }, /* P00: 1st (left) USB3 (OC #0) */
+ { 1, 1, 0 }, /* P01: 2nd (left) USB3 (OC #0) */
+ { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */
+ { 1, 1, 1 }, /* P03: 2nd Multibay USB3 (OC #1) */
+ { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */
+ { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */
+ { 1, 0, 8 }, /* P06: USB Hub x4 USB2 (no OC) */
+ { 1, 0, 8 }, /* P07: MiniPCIe 4 USB2 (no OC) */
+ { 1, 1, 8 }, /* P08: SD card reader USB2 (no OC) */
+ { 1, 1, 4 }, /* P09: 3rd (right) USB2 (OC #4) */
+ { 1, 0, 5 }, /* P10: 4th (right) USB2 (OC #5) */
+ { 1, 0, 8 }, /* P11: 3rd Multibay USB2 (no OC) */
+ { 1, 1, 8 }, /* P12: misc internal USB2 (no OC) */
+ { 1, 1, 6 }, /* P13: misc internal USB2 (OC #6) */
+};
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}