tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index ecad52e..1bce4b2 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -14,20 +14,6 @@
# CNVi BT enable/disable
register "CnviBtCore" = "true"
- register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
- register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN
- register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth
- register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
- register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2
- register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3
- register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4
- register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
- register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port3
- register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port4
-
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
-
# CPU replacement check
register "CpuReplacementCheck" = "1"
@@ -206,7 +192,25 @@
end
device ref gspi2 off end
device ref gspi3 off end
- device ref south_xhci on end
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC0), // Type-C Port1
+ [1] = USB2_PORT_EMPTY, // M.2 WWAN
+ [2] = USB2_PORT_MID(OC3), // M.2 Bluetooth
+ [3] = USB2_PORT_MID(OC0), // USB3/2 Type A port1
+ [4] = USB2_PORT_MID(OC0), // Type-C Port2
+ [5] = USB2_PORT_MID(OC3), // Type-C Port3
+ [6] = USB2_PORT_MID(OC3), // Type-C Port4
+ [7] = USB2_PORT_MID(OC0), // USB3/2 Type A port2
+ [8] = USB2_PORT_MID(OC3), // USB2 Type A port3
+ [9] = USB2_PORT_MID(OC3), // USB2 Type A port4
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC0), // USB3/2 Type A port1
+ [1] = USB3_PORT_DEFAULT(OC0), // USB3/2 Type A port2
+ }"
+ end
device ref south_xdci on end
device ref shared_ram on end
device ref cnvi_wifi on