tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 8bf1c7d..0b3568b 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -90,19 +90,6 @@
# FSP configuration
register "SaGv" = "SaGv_Enabled"
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
- register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Cl
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
- register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Co
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
-
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera
-
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)"
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)"
@@ -437,7 +424,24 @@
end # DPTF 0x9A03
device ref gna on end
device ref north_xhci on end
- device ref south_xhci on end
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), // Type-A Port A0
+ [1] = USB2_PORT_MID(OC_SKIP), // Type-A Port A1
+ [2] = USB2_PORT_MID(OC_SKIP), // M.2 WWAN
+ [3] = USB2_PORT_MID(OC_SKIP), // Type-A / Type-C Cl
+ [4] = USB2_PORT_MID(OC_SKIP), // M.2 Camera
+ [8] = USB2_PORT_MID(OC_SKIP), // Type-A / Type-C Co
+ [9] = USB2_PORT_MID(OC_SKIP), // M.2 Bluetooth
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC1), // USB3/2 Type A port A0
+ [1] = USB3_PORT_DEFAULT(OC2), // USB3/2 Type A port A1
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // M.2 WWAN
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // M.2 Camera
+ }"
+ end
device ref shared_ram on end
device ref cnvi_wifi on
chip drivers/wifi/generic