cpu/intel/car/p4-netburst: Prepare for x86_64
Use proper car symbols.
Change-Id: I169fd6020e5b81da66dbe4fe83ba446eedc882e9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56018
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 103d9e9..71ec9e3 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -11,6 +11,8 @@
.section .init
.global bootblock_pre_c_entry
+#include <cpu/intel/car/cache_as_ram_symbols.inc>
+
.code32
_cache_as_ram_setup:
@@ -212,7 +214,7 @@
/* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx
- movl $_car_mtrr_start, %eax
+ movl car_mtrr_start, %eax
orl $MTRR_TYPE_WRBACK, %eax
xorl %edx, %edx
wrmsr
@@ -220,7 +222,7 @@
/* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr
- movl $_car_mtrr_mask, %eax
+ movl car_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
@@ -272,12 +274,12 @@
/* Cache the whole rom to fetch microcode updates */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
- movl $_rom_mtrr_base, %eax
+ movl rom_mtrr_base, %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx
rdmsr
- movl $_rom_mtrr_mask, %eax
+ movl rom_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
@@ -324,12 +326,12 @@
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
movl $_program, %eax
- andl $_xip_mtrr_mask, %eax
+ andl xip_mtrr_mask, %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx
rdmsr
- movl $_xip_mtrr_mask, %eax
+ movl xip_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr