tree 37b10c4e7ccb94f534f4d7cd6ea368db8841a042
parent dccfb8a2158287be48522f9f70fd3e83b84c671f
author Michał Żygowski <michal.zygowski@3mdeb.com> 1649337035 +0200
committer Michał Żygowski <michal.zygowski@3mdeb.com> 1649666914 +0000

soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding

Some Super I/Os may be strapped to respond on the secondary ports
0x4e/0x4f. Enable them early so that mainboard is able to initialize
a serial port for example.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6df158f54a48fb9f3173a4b209316c8116aa265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>