soc/amd/stoneyridge/lpc.c: Fix bit definitions
The latest public BKDG (3.6) releases some previously undefined (reserved)
bits, also some bits were wrongly named (possibly copied from previous chip).
Fix these definitions, including the header file where they are defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index 10f4a4b..eb51281 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -76,11 +76,12 @@
pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte);
/*
- * bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12.
- * todo: verify against BKDG
+ * IMC is not used, but some of its registers and ports need to be
+ * programmed/accessed. So enable CPU access to them. This fixes
+ * SPI_CS# timing issue when running at 66MHz.
*/
byte = pci_read_config8(dev, LPC_HOST_CONTROL);
- byte |= SPI_FROM_HOST_PREFETCH_EN | 1 << 3;
+ byte |= IMC_PAGE_FROM_HOST_EN | IMC_PORT_FROM_HOST_EN;
pci_write_config8(dev, LPC_HOST_CONTROL, byte);
cmos_check_update_date();