nb/intel/x4x: Define and use MMCONF_BUS_NUMBER
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Moreover, the ASL reservation for MMCONFIG was only for 64 busses.
Change-Id: I7366a5096aacd92401535be020358447650b4247
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index bdef6f2..32e85d3 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -25,6 +25,10 @@
config MMCONF_BASE_ADDRESS
default 0xe0000000
+config MMCONF_BUS_NUMBER
+ int
+ default 256
+
config SMM_RESERVED_SIZE
hex
default 0x100000
diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c
index 4088e75..8f94b34 100644
--- a/src/northbridge/intel/x4x/acpi.c
+++ b/src/northbridge/intel/x4x/acpi.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <types.h>
#include <console/console.h>
#include <acpi/acpi.h>
#include <acpi/acpigen.h>
@@ -9,13 +8,8 @@
unsigned long acpi_fill_mcfg(unsigned long current)
{
- u32 pciexbar, length;
-
- if (!decode_pcie_bar(&pciexbar, &length))
- return current;
-
- current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
- pciexbar, 0x0, 0x0, (length >> 20) - 1);
+ current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
+ CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}
diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl
index b013da7..33cb7ad 100644
--- a/src/northbridge/intel/x4x/acpi/x4x.asl
+++ b/src/northbridge/intel/x4x/acpi/x4x.asl
@@ -15,7 +15,7 @@
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
+ Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index 1192fdb..f15d181 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -2,15 +2,27 @@
#include <arch/bootblock.h>
#include <arch/mmio.h>
+#include <assert.h>
#include <device/pci_ops.h>
+#include <types.h>
#include "x4x.h"
+static uint32_t encode_pciexbar_length(void)
+{
+ switch (CONFIG_MMCONF_BUS_NUMBER) {
+ case 256: return 0 << 1;
+ case 128: return 1 << 1;
+ case 64: return 2 << 1;
+ default: return dead_code_t(uint32_t);
+ }
+}
+
void bootblock_early_northbridge_init(void)
{
/* Disable LaGrande Technology (LT) */
read32((void *)TPM_BASE_ADDRESS);
- const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1;
+ const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);
}
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index aa737f3..5114e0b 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -57,42 +57,6 @@
}
}
-int decode_pcie_bar(u32 *const base, u32 *const len)
-{
- *base = 0;
- *len = 0;
-
- const struct {
- u16 num_buses;
- u32 addr_mask;
- } busmask[] = {
- {256, 0xf0000000},
- {128, 0xf8000000},
- {64, 0xfc000000},
- {0, 0},
- };
-
- const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO);
-
- if (!(pciexbar_reg & 1)) {
- printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
- return 0;
- }
-
- const u32 index = (pciexbar_reg >> 1) & 3;
- const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask;
- const int max_buses = busmask[index].num_buses;
-
- if (!pciexbar) {
- printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");
- return 0;
- }
-
- *base = pciexbar;
- *len = max_buses << 20;
- return 1;
-}
-
static size_t northbridge_get_tseg_size(void)
{
const u8 esmramc = pci_read_config8(HOST_BRIDGE, D0F0_ESMRAMC);
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 5e46270..de60338 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -20,7 +20,6 @@
u8 index;
u64 tom, touud;
u32 tomk, tolud, delta_cbmem;
- u32 pcie_config_base, pcie_config_size;
u32 uma_sizek = 0;
const u32 top32memk = 4 * (GiB / KiB);
@@ -111,12 +110,7 @@
top32memk - (DEFAULT_HECIBAR >> 10),
IORESOURCE_RESERVE);
- if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) {
- printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
- "size=0x%x\n", pcie_config_base, pcie_config_size);
- fixed_mem_resource(dev, index++, pcie_config_base >> 10,
- pcie_config_size >> 10, IORESOURCE_RESERVE);
- }
+ mmconf_resource(dev, index++);
}
static void mch_domain_set_resources(struct device *dev)
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index ea34fe0..33f7a4c 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -172,7 +172,6 @@
u32 decode_igd_memory_size(u32 gms);
u32 decode_igd_gtt_size(u32 gsm);
u32 decode_tseg_size(const u32 esmramc);
-int decode_pcie_bar(u32 *const base, u32 *const len);
#include <device/device.h>
struct acpi_rsdp;