mb/google/poppy/variants/nocturne: enable I2C #5 bus

Enable I2C #5 for rear camera and SAR.

BUG=b:79784124
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage' and verify i2c bus #5
is detected.

Change-Id: Ic5b754fb97231aeab0278d71f8ced9343c30feda
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 6feb3375..621bbe4 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -197,7 +197,7 @@
 		},
 	}"
 
-	# Camera
+	# Front Camera
 	register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
 	register "i2c[3]" = "{
 		.speed = I2C_SPEED_FAST,
@@ -217,6 +217,14 @@
 		}
 	}"
 
+	# Rear Camera & SAR
+	register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"
+	register "i2c[5]" = "{
+		.speed = I2C_SPEED_FAST,
+		.rise_time_ns = 98,
+		.fall_time_ns = 38,
+	}"
+
 	# GSPI0 for cr50 TPM
 	register "gspi[0]" = "{
 		 .speed_mhz = 1,
@@ -229,7 +237,7 @@
 		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
 		[PchSerialIoIndexSpi0]  = PchSerialIoPci,
 		[PchSerialIoIndexSpi1]  = PchSerialIoPci,
 		[PchSerialIoIndexUart0] = PchSerialIoSkipInit,
@@ -272,7 +280,7 @@
 		device pci 16.4 off end # Management Engine Interface 3
 		device pci 17.0 off end # SATA
 		device pci 19.0 on  end # UART #2
-		device pci 19.1 off end # I2C #5
+		device pci 19.1 on  end # I2C #5
 		device pci 19.2 on
 			chip drivers/i2c/max98373
 				register "vmon_slot_no" = "4"