diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
index 1a32ef3..947eba9 100644
--- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
@@ -72,81 +72,12 @@
  */
 
 /*  Default sockets to off  */
-#define OPTION_G34_SOCKET_SUPPORT    FALSE
-#define OPTION_C32_SOCKET_SUPPORT    FALSE
-#define OPTION_S1G3_SOCKET_SUPPORT   FALSE
-#define OPTION_S1G4_SOCKET_SUPPORT   FALSE
-#define OPTION_ASB2_SOCKET_SUPPORT   FALSE
-#define OPTION_FS1_SOCKET_SUPPORT    FALSE
-#define OPTION_FM1_SOCKET_SUPPORT    FALSE
-#define OPTION_FP1_SOCKET_SUPPORT    FALSE
 #define OPTION_FT1_SOCKET_SUPPORT    FALSE
-#define OPTION_AM3_SOCKET_SUPPORT    FALSE
 
 /*  Default families to off  */
-#define OPTION_FAMILY10H             FALSE
-#define OPTION_FAMILY12H             FALSE
 #define OPTION_FAMILY14H             FALSE
-#define OPTION_FAMILY15H             FALSE
-
 
 /*  Enable the appropriate socket support  */
-#ifdef INSTALL_G34_SOCKET_SUPPORT
-  #if  INSTALL_G34_SOCKET_SUPPORT == TRUE
-    #undef OPTION_G34_SOCKET_SUPPORT
-    #define OPTION_G34_SOCKET_SUPPORT  TRUE
-  #endif
-#endif
-
-#ifdef INSTALL_C32_SOCKET_SUPPORT
-  #if  INSTALL_C32_SOCKET_SUPPORT == TRUE
-    #undef OPTION_C32_SOCKET_SUPPORT
-    #define OPTION_C32_SOCKET_SUPPORT  TRUE
-  #endif
-#endif
-
-#ifdef INSTALL_S1G3_SOCKET_SUPPORT
-  #if  INSTALL_S1G3_SOCKET_SUPPORT == TRUE
-    #undef OPTION_S1G3_SOCKET_SUPPORT
-    #define OPTION_S1G3_SOCKET_SUPPORT  TRUE
-  #endif
-#endif
-
-#ifdef INSTALL_S1G4_SOCKET_SUPPORT
-  #if  INSTALL_S1G4_SOCKET_SUPPORT == TRUE
-    #undef OPTION_S1G4_SOCKET_SUPPORT
-    #define OPTION_S1G4_SOCKET_SUPPORT  TRUE
-  #endif
-#endif
-
-#ifdef INSTALL_ASB2_SOCKET_SUPPORT
-  #if  INSTALL_ASB2_SOCKET_SUPPORT == TRUE
-    #undef OPTION_ASB2_SOCKET_SUPPORT
-    #define OPTION_ASB2_SOCKET_SUPPORT  TRUE
-  #endif
-#endif
-
-#ifdef INSTALL_FS1_SOCKET_SUPPORT
-  #if  INSTALL_FS1_SOCKET_SUPPORT == TRUE
-    #undef OPTION_FS1_SOCKET_SUPPORT
-    #define OPTION_FS1_SOCKET_SUPPORT  TRUE
-  #endif
-#endif
-
-#ifdef INSTALL_FM1_SOCKET_SUPPORT
-  #if  INSTALL_FM1_SOCKET_SUPPORT == TRUE
-    #undef OPTION_FM1_SOCKET_SUPPORT
-    #define OPTION_FM1_SOCKET_SUPPORT  TRUE
-  #endif
-#endif
-
-#ifdef INSTALL_FP1_SOCKET_SUPPORT
-  #if  INSTALL_FP1_SOCKET_SUPPORT == TRUE
-    #undef OPTION_FP1_SOCKET_SUPPORT
-    #define OPTION_FP1_SOCKET_SUPPORT  TRUE
-  #endif
-#endif
-
 #ifdef INSTALL_FT1_SOCKET_SUPPORT
   #if  INSTALL_FT1_SOCKET_SUPPORT == TRUE
     #undef OPTION_FT1_SOCKET_SUPPORT
@@ -154,31 +85,6 @@
   #endif
 #endif
 
-#ifdef INSTALL_AM3_SOCKET_SUPPORT
-  #if  INSTALL_AM3_SOCKET_SUPPORT == TRUE
-    #undef OPTION_AM3_SOCKET_SUPPORT
-    #define OPTION_AM3_SOCKET_SUPPORT  TRUE
-  #endif
-#endif
-
-
-/*  Enable the appropriate family support  */
-// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3
-#ifdef INSTALL_FAMILY_10_SUPPORT
-  #if  INSTALL_FAMILY_10_SUPPORT == TRUE
-    #undef OPTION_FAMILY10H
-    #define OPTION_FAMILY10H     TRUE
-  #endif
-#endif
-
-// F12 is supported in FP1, FS1, & FM1
-#ifdef INSTALL_FAMILY_12_SUPPORT
-  #if  INSTALL_FAMILY_12_SUPPORT == TRUE
-    #undef OPTION_FAMILY12H
-    #define OPTION_FAMILY12H     TRUE
-  #endif
-#endif
-
 // F14 is supported in FT1
 #ifdef INSTALL_FAMILY_14_SUPPORT
   #if  INSTALL_FAMILY_14_SUPPORT == TRUE
@@ -187,30 +93,6 @@
   #endif
 #endif
 
-// F15 is supported in G34, C32, & AM3
-#ifdef INSTALL_FAMILY_15_SUPPORT
-  #if  INSTALL_FAMILY_15_SUPPORT == TRUE
-    #undef OPTION_FAMILY15H
-    #define OPTION_FAMILY15H     TRUE
-  #endif
-#endif
-
-
-/*  Turn off families not required by socket designations */
-#if (OPTION_FAMILY10H == TRUE)
-  #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
-    #undef OPTION_FAMILY10H
-    #define OPTION_FAMILY10H  FALSE
-  #endif
-#endif
-
-#if (OPTION_FAMILY12H == TRUE)
-  #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE)
-    #undef OPTION_FAMILY12H
-    #define OPTION_FAMILY12H  FALSE
-  #endif
-#endif
-
 #if (OPTION_FAMILY14H == TRUE)
   #if (OPTION_FT1_SOCKET_SUPPORT == FALSE)
     #undef OPTION_FAMILY14H
@@ -218,62 +100,8 @@
   #endif
 #endif
 
-#if (OPTION_FAMILY15H == TRUE)
-  #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
-    #undef OPTION_FAMILY15H
-    #define OPTION_FAMILY15H  FALSE
-  #endif
-#endif
-
 
 /*  Check for invalid combinations of socket/family */
-#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
-    #error No G34 supported families included in the build
-  #endif
-#endif
-
-#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
-    #error No C32 supported families included in the build
-  #endif
-#endif
-
-#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY10H == FALSE)
-    #error No S1G3 supported families included in the build
-  #endif
-#endif
-
-#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY10H == FALSE)
-    #error No S1G4 supported families included in the build
-  #endif
-#endif
-
-#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY10H == FALSE)
-    #error No ASB2 supported families included in the build
-  #endif
-#endif
-
-#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY12H == FALSE)
-    #error No FS1 supported families included in the build
-  #endif
-#endif
-
-#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY12H == FALSE)
-    #error No FM1 supported families included in the build
-  #endif
-#endif
-
-#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY12H == FALSE)
-    #error No FP1 supported families included in the build
-  #endif
-#endif
 
 #if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
   #if (OPTION_FAMILY14H == FALSE)
@@ -281,13 +109,6 @@
   #endif
 #endif
 
-#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
-    #error No AM3 supported families included in the build
-  #endif
-#endif
-
-
 /* Process AGESA private data
  *
  * Turn on appropriate CPU models and memory controllers,
@@ -295,26 +116,10 @@
  */
 
 /*  Default all models to off  */
-#define OPTION_FAMILY10H_BL          FALSE
-#define OPTION_FAMILY10H_DA          FALSE
-#define OPTION_FAMILY10H_HY          FALSE
-#define OPTION_FAMILY10H_PH          FALSE
-#define OPTION_FAMILY10H_RB          FALSE
-#define OPTION_FAMILY12H_LN          FALSE
 #define OPTION_FAMILY14H_ON          FALSE
-#define OPTION_FAMILY15H_OR          FALSE
 
 /*  Default all memory controllers to off  */
-#define OPTION_MEMCTLR_DR            FALSE
-#define OPTION_MEMCTLR_HY            FALSE
-#define OPTION_MEMCTLR_OR            FALSE
-#define OPTION_MEMCTLR_C32           FALSE
-#define OPTION_MEMCTLR_DA            FALSE
-#define OPTION_MEMCTLR_LN            FALSE
 #define OPTION_MEMCTLR_ON            FALSE
-#define OPTION_MEMCTLR_Ni            FALSE
-#define OPTION_MEMCTLR_PH            FALSE
-#define OPTION_MEMCTLR_RB            FALSE
 
 /*  Default all memory controls to off  */
 #define OPTION_HW_WRITE_LEV_TRAINING            FALSE
@@ -364,551 +169,6 @@
 #define OPTION_GFX_RECOVERY                     FALSE
 
 /*  Enable all private controls based on socket/family enables  */
-#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY10H == TRUE)
-    #undef OPTION_FAMILY10H_HY
-    #define OPTION_FAMILY10H_HY  TRUE
-    #undef OPTION_MEMCTLR_HY
-    #define OPTION_MEMCTLR_HY    TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
-    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_MULTISOCKET
-    #define OPTION_MULTISOCKET  TRUE
-    #undef OPTION_SRAT
-    #define OPTION_SRAT  TRUE
-    #undef OPTION_SLIT
-    #define OPTION_SLIT  TRUE
-    #undef OPTION_HT_ASSIST
-    #define OPTION_HT_ASSIST  TRUE
-    #undef OPTION_CPU_CORELEVLING
-    #define OPTION_CPU_CORELEVLING  TRUE
-    #undef OPTION_MSG_BASED_C1E
-    #define OPTION_MSG_BASED_C1E  TRUE
-    #undef OPTION_CPU_CFOH
-    #define OPTION_CPU_CFOH  TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_RDIMMS
-    #define OPTION_RDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_ECC
-    #define OPTION_ECC  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE  TRUE
-    #undef OPTION_NODE_INTERLEAVE
-    #define OPTION_NODE_INTERLEAVE  TRUE
-    #undef OPTION_PARALLEL_TRAINING
-    #define OPTION_PARALLEL_TRAINING  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-  #endif
-  #if (OPTION_FAMILY15H == TRUE)
-    #undef OPTION_FAMILY15H_OR
-    #define OPTION_FAMILY15H_OR  TRUE
-    #undef OPTION_MEMCTLR_OR
-    #define OPTION_MEMCTLR_OR    TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_CONTINOUS_PATTERN_GENERATION
-    #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
-    #undef OPTION_HW_DQS_REC_EN_TRAINING
-    #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
-    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_MULTISOCKET
-    #define OPTION_MULTISOCKET  TRUE
-    #undef OPTION_C6_STATE
-    #define OPTION_C6_STATE  TRUE
-    #undef OPTION_IO_CSTATE
-    #define OPTION_IO_CSTATE TRUE
-    #undef OPTION_CPB
-    #define OPTION_CPB  TRUE
-    #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
-    #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
-    #undef OPTION_SRAT
-    #define OPTION_SRAT  TRUE
-    #undef OPTION_SLIT
-    #define OPTION_SLIT  TRUE
-    #undef OPTION_HT_ASSIST
-    #define OPTION_HT_ASSIST  TRUE
-    #undef OPTION_ATM_MODE
-    #define OPTION_ATM_MODE  TRUE
-    #undef OPTION_CPU_CORELEVLING
-    #define OPTION_CPU_CORELEVLING  TRUE
-    #undef OPTION_MSG_BASED_C1E
-    #define OPTION_MSG_BASED_C1E  TRUE
-    #undef OPTION_CPU_CFOH
-    #define OPTION_CPU_CFOH  TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_RDIMMS
-    #define OPTION_RDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_LRDIMMS
-    #define OPTION_LRDIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_ECC
-    #define OPTION_ECC  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE  TRUE
-    #undef OPTION_NODE_INTERLEAVE
-    #define OPTION_NODE_INTERLEAVE  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-  #endif
-#endif
-
-#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY10H == TRUE)
-    #undef OPTION_FAMILY10H_HY
-    #define OPTION_FAMILY10H_HY  TRUE
-    #undef OPTION_MEMCTLR_C32
-    #define OPTION_MEMCTLR_C32   TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
-    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_ADDR_TO_CS_TRANSLATOR
-    #define OPTION_ADDR_TO_CS_TRANSLATOR  FALSE
-    #undef OPTION_MULTISOCKET
-    #define OPTION_MULTISOCKET  TRUE
-    #undef OPTION_SRAT
-    #define OPTION_SRAT  TRUE
-    #undef OPTION_SLIT
-    #define OPTION_SLIT  TRUE
-    #undef OPTION_HT_ASSIST
-    #define OPTION_HT_ASSIST  TRUE
-    #undef OPTION_CPU_CORELEVLING
-    #define OPTION_CPU_CORELEVLING  TRUE
-    #undef OPTION_MSG_BASED_C1E
-    #define OPTION_MSG_BASED_C1E  TRUE
-    #undef OPTION_CPU_CFOH
-    #define OPTION_CPU_CFOH  TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_RDIMMS
-    #define OPTION_RDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_ECC
-    #define OPTION_ECC  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE  TRUE
-    #undef OPTION_NODE_INTERLEAVE
-    #define OPTION_NODE_INTERLEAVE  TRUE
-    #undef OPTION_PARALLEL_TRAINING
-    #define OPTION_PARALLEL_TRAINING  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-  #endif
-  #if (OPTION_FAMILY15H == TRUE)
-    #undef OPTION_FAMILY15H_OR
-    #define OPTION_FAMILY15H_OR  TRUE
-    #undef OPTION_MEMCTLR_OR
-    #define OPTION_MEMCTLR_OR    TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_CONTINOUS_PATTERN_GENERATION
-    #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
-    #undef OPTION_HW_DQS_REC_EN_TRAINING
-    #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
-    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_ADDR_TO_CS_TRANSLATOR
-    #define OPTION_ADDR_TO_CS_TRANSLATOR  TRUE
-    #undef OPTION_MULTISOCKET
-    #define OPTION_MULTISOCKET  TRUE
-    #undef OPTION_C6_STATE
-    #define OPTION_C6_STATE  TRUE
-    #undef OPTION_IO_CSTATE
-    #define OPTION_IO_CSTATE TRUE
-    #undef OPTION_CPB
-    #define OPTION_CPB  TRUE
-    #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
-    #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
-    #undef OPTION_SRAT
-    #define OPTION_SRAT  TRUE
-    #undef OPTION_SLIT
-    #define OPTION_SLIT  TRUE
-    #undef OPTION_HT_ASSIST
-    #define OPTION_HT_ASSIST  TRUE
-    #undef OPTION_ATM_MODE
-    #define OPTION_ATM_MODE  TRUE
-    #undef OPTION_CPU_CORELEVLING
-    #define OPTION_CPU_CORELEVLING  TRUE
-    #undef OPTION_MSG_BASED_C1E
-    #define OPTION_MSG_BASED_C1E  TRUE
-    #undef OPTION_CPU_CFOH
-    #define OPTION_CPU_CFOH  TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_RDIMMS
-    #define OPTION_RDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_LRDIMMS
-    #define OPTION_LRDIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_ECC
-    #define OPTION_ECC  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE  TRUE
-    #undef OPTION_NODE_INTERLEAVE
-    #define OPTION_NODE_INTERLEAVE  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-  #endif
-#endif
-
-#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY10H == TRUE)
-    #undef OPTION_FAMILY10H_BL
-    #define OPTION_FAMILY10H_BL  TRUE
-    #undef OPTION_FAMILY10H_DA
-    #define OPTION_FAMILY10H_DA  TRUE
-    #undef OPTION_MEMCTLR_DA
-    #define OPTION_MEMCTLR_DA    TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
-    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_CPU_CORELEVLING
-    #define OPTION_CPU_CORELEVLING  TRUE
-    #undef OPTION_CPU_CFOH
-    #define OPTION_CPU_CFOH  TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_ECC
-    #define OPTION_ECC  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE  TRUE
-    #undef OPTION_NODE_INTERLEAVE
-    #define OPTION_NODE_INTERLEAVE  TRUE
-    #undef OPTION_PARALLEL_TRAINING
-    #define OPTION_PARALLEL_TRAINING  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-  #endif
-#endif
-
-#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY10H == TRUE)
-    #undef OPTION_FAMILY10H_BL
-    #define OPTION_FAMILY10H_BL  TRUE
-    #undef OPTION_FAMILY10H_DA
-    #define OPTION_FAMILY10H_DA  TRUE
-    #undef OPTION_MEMCTLR_DA
-    #define OPTION_MEMCTLR_DA    TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
-    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_CPU_CORELEVLING
-    #define OPTION_CPU_CORELEVLING  TRUE
-    #undef OPTION_CPU_CFOH
-    #define OPTION_CPU_CFOH  TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_ECC
-    #define OPTION_ECC  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE  TRUE
-    #undef OPTION_NODE_INTERLEAVE
-    #define OPTION_NODE_INTERLEAVE  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-  #endif
-#endif
-
-#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY10H == TRUE)
-    #undef OPTION_FAMILY10H_BL
-    #define OPTION_FAMILY10H_BL  TRUE
-    #undef OPTION_FAMILY10H_DA
-    #define OPTION_FAMILY10H_DA  TRUE
-    #undef OPTION_MEMCTLR_Ni
-    #define OPTION_MEMCTLR_Ni    TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
-    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_CPU_CORELEVLING
-    #define OPTION_CPU_CORELEVLING  TRUE
-    #undef OPTION_CPU_CFOH
-    #define OPTION_CPU_CFOH  TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_ECC
-    #define OPTION_ECC  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE  TRUE
-    #undef OPTION_NODE_INTERLEAVE
-    #define OPTION_NODE_INTERLEAVE  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-  #endif
-#endif
-
-#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY12H == TRUE)
-    #undef OPTION_FAMILY12H_LN
-    #define OPTION_FAMILY12H_LN  TRUE
-    #undef OPTION_MEMCTLR_LN
-    #define OPTION_MEMCTLR_LN    TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_CONTINOUS_PATTERN_GENERATION
-    #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
-    #undef OPTION_HW_DQS_REC_EN_TRAINING
-    #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_GFX_RECOVERY
-    #define OPTION_GFX_RECOVERY  TRUE
-    #undef OPTION_C6_STATE
-    #define OPTION_C6_STATE  TRUE
-    #undef OPTION_IO_CSTATE
-    #define OPTION_IO_CSTATE TRUE
-    #undef OPTION_CPB
-    #define OPTION_CPB  TRUE
-    #undef OPTION_S3SCRIPT
-    #define OPTION_S3SCRIPT  TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-  #endif
-#endif
-
-#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY12H == TRUE)
-    #undef OPTION_FAMILY12H_LN
-    #define OPTION_FAMILY12H_LN  TRUE
-    #undef OPTION_MEMCTLR_LN
-    #define OPTION_MEMCTLR_LN    TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_CONTINOUS_PATTERN_GENERATION
-    #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
-    #undef OPTION_HW_DQS_REC_EN_TRAINING
-    #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_GFX_RECOVERY
-    #define OPTION_GFX_RECOVERY  TRUE
-    #undef OPTION_C6_STATE
-    #define OPTION_C6_STATE  TRUE
-    #undef OPTION_IO_CSTATE
-    #define OPTION_IO_CSTATE TRUE
-    #undef OPTION_CPB
-    #define OPTION_CPB  TRUE
-    #undef OPTION_S3SCRIPT
-    #define OPTION_S3SCRIPT  TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-  #endif
-#endif
-
-#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY12H == TRUE)
-    #undef OPTION_FAMILY12H_LN
-    #define OPTION_FAMILY12H_LN  TRUE
-    #undef OPTION_MEMCTLR_LN
-    #define OPTION_MEMCTLR_LN    TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_CONTINOUS_PATTERN_GENERATION
-    #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
-    #undef OPTION_HW_DQS_REC_EN_TRAINING
-    #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_ADDR_TO_CS_TRANSLATOR
-    #define OPTION_ADDR_TO_CS_TRANSLATOR  TRUE
-    #undef OPTION_GFX_RECOVERY
-    #define OPTION_GFX_RECOVERY  TRUE
-    #undef OPTION_C6_STATE
-    #define OPTION_C6_STATE  TRUE
-    #undef OPTION_IO_CSTATE
-    #define OPTION_IO_CSTATE TRUE
-    #undef OPTION_CPB
-    #define OPTION_CPB  TRUE
-    #undef OPTION_S3SCRIPT
-    #define OPTION_S3SCRIPT  TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-  #endif
-#endif
 
 #if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
   #if (OPTION_FAMILY14H == TRUE)
@@ -955,128 +215,7 @@
   #endif
 #endif
 
-#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY10H == TRUE)
-    #undef OPTION_FAMILY10H_BL
-    #define OPTION_FAMILY10H_BL  TRUE
-    #undef OPTION_FAMILY10H_DA
-    #define OPTION_FAMILY10H_DA  TRUE
-    #undef OPTION_FAMILY10H_PH
-    #define OPTION_FAMILY10H_PH  TRUE
-    #undef OPTION_FAMILY10H_RB
-    #define OPTION_FAMILY10H_RB  TRUE
-    #undef OPTION_MEMCTLR_RB
-    #define OPTION_MEMCTLR_RB   TRUE
-    #undef OPTION_MEMCTLR_DA
-    #define OPTION_MEMCTLR_DA   TRUE
-    #undef OPTION_MEMCTLR_PH
-    #define OPTION_MEMCTLR_PH   TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
-    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_CPU_CORELEVLING
-    #define OPTION_CPU_CORELEVLING  TRUE
-    #undef OPTION_CPU_CFOH
-    #define OPTION_CPU_CFOH  TRUE
-    #undef OPTION_IO_CSTATE
-    #define OPTION_IO_CSTATE TRUE
-    #undef OPTION_CPB
-    #define OPTION_CPB  TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_ECC
-    #define OPTION_ECC  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE  TRUE
-    #undef OPTION_NODE_INTERLEAVE
-    #define OPTION_NODE_INTERLEAVE  TRUE
-    #undef OPTION_PARALLEL_TRAINING
-    #define OPTION_PARALLEL_TRAINING  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-  #endif
-  #if (OPTION_FAMILY15H == TRUE)
-    #undef OPTION_FAMILY15H_OR
-    #define OPTION_FAMILY15H_OR  TRUE
-    #undef OPTION_MEMCTLR_OR
-    #define OPTION_MEMCTLR_OR    TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_CONTINOUS_PATTERN_GENERATION
-    #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
-    #undef OPTION_HW_DQS_REC_EN_TRAINING
-    #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_C6_STATE
-    #define OPTION_C6_STATE  TRUE
-    #undef OPTION_IO_CSTATE
-    #define OPTION_IO_CSTATE TRUE
-    #undef OPTION_CPB
-    #define OPTION_CPB  TRUE
-    #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
-    #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_ADDR_TO_CS_TRANSLATOR
-    #define OPTION_ADDR_TO_CS_TRANSLATOR  TRUE
-    #undef OPTION_CPU_CORELEVLING
-    #define OPTION_CPU_CORELEVLING  TRUE
-    #undef OPTION_CPU_CFOH
-    #define OPTION_CPU_CFOH  TRUE
-    #undef OPTION_MSG_BASED_C1E
-    #define OPTION_MSG_BASED_C1E  TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_RDIMMS
-    #define OPTION_RDIMMS  TRUE
-    #undef OPTION_LRDIMMS
-    #define OPTION_LRDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_ECC
-    #define OPTION_ECC  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE  TRUE
-    #undef OPTION_NODE_INTERLEAVE
-    #define OPTION_NODE_INTERLEAVE  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-  #endif
-#endif
-
-#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
+#if (OPTION_FAMILY14H == TRUE)
   #undef  GNB_SUPPORT
   #define GNB_SUPPORT   TRUE
 #endif