AGESA f14 vendorcode: Only have f14 Ontario config
Change-Id: I8cf2f23d785e934371dfa687483491cd22b9863d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionC6Install.h b/src/vendorcode/amd/agesa/f14/Config/OptionC6Install.h
index ea67863..14b15ad 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionC6Install.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionC6Install.h
@@ -54,39 +54,10 @@
* Check to validate the definition
*/
#define OPTION_C6_STATE_FEAT
-#define F12_C6_STATE_SUPPORT
#define F14_C6_STATE_SUPPORT
-#define F15_C6_STATE_SUPPORT
#if OPTION_C6_STATE == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
- #ifdef OPTION_FAMILY12H
- #if OPTION_FAMILY12H == TRUE
- #if OPTION_FAMILY12H_LN == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
- #undef OPTION_C6_STATE_FEAT
- #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
- extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support;
- #undef F12_C6_STATE_SUPPORT
- #define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support},
-
- #if OPTION_EARLY_SAMPLES == TRUE
- extern F_F12_ES_C6_INIT F12C6A0Workaround;
-
- CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
- {
- F12C6A0Workaround
- };
- #else
- CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
- {
- (PF_F12_ES_C6_INIT) CommonVoid
- };
- #endif
-
- #endif
- #endif
- #endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
@@ -119,26 +90,12 @@
#endif
#endif
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- #if OPTION_FAMILY15H_OR == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
- #undef OPTION_C6_STATE_FEAT
- #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
- extern CONST C6_FAMILY_SERVICES ROMDATA F15C6Support;
- #undef F15_C6_STATE_SUPPORT
- #define F15_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15C6Support},
- #endif
- #endif
- #endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
{
- F12_C6_STATE_SUPPORT
F14_C6_STATE_SUPPORT
- F15_C6_STATE_SUPPORT
{0, NULL}
};
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionCpbInstall.h
index 79261de..4c9cf4c 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionCpbInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionCpbInstall.h
@@ -54,40 +54,10 @@
* Check to validate the definition
*/
#define OPTION_CPB_FEAT
-#define F10_CPB_SUPPORT
-#define F12_CPB_SUPPORT
#define F14_ON_CPB_SUPPORT
-#define F15_CPB_SUPPORT
#if OPTION_CPB == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
- // Family 10h
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_FAMILY10H_PH == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
- #undef OPTION_CPB_FEAT
- #define OPTION_CPB_FEAT &CpuFeatureCpb,
- extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport;
- #undef F10_CPB_SUPPORT
- #define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport},
- #endif
- #endif
- #endif
-
- // Family 12h
- #ifdef OPTION_FAMILY12H
- #if OPTION_FAMILY12H == TRUE
- #if OPTION_FAMILY12H_LN == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
- #undef OPTION_CPB_FEAT
- #define OPTION_CPB_FEAT &CpuFeatureCpb,
- extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport;
- #undef F12_CPB_SUPPORT
- #define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport},
- #endif
- #endif
- #endif
// Family 14h
#ifdef OPTION_FAMILY14H
@@ -103,29 +73,12 @@
#endif
#endif
- // Family 15h
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- #if OPTION_FAMILY15H_OR == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
- #undef OPTION_CPB_FEAT
- #define OPTION_CPB_FEAT &CpuFeatureCpb,
- extern CONST CPB_FAMILY_SERVICES ROMDATA F15CpbSupport;
- #undef F15_CPB_SUPPORT
- #define F15_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15CpbSupport},
- #endif
- #endif
- #endif
-
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
{
- F10_CPB_SUPPORT
- F12_CPB_SUPPORT
F14_ON_CPB_SUPPORT
- F15_CPB_SUPPORT
{0, NULL}
};
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionCpuCacheFlushOnHaltInstall.h
index 8d6e454..42adc64 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionCpuCacheFlushOnHaltInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionCpuCacheFlushOnHaltInstall.h
@@ -54,63 +54,13 @@
* Check to validate the definition
*/
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
-#define F10_BL_CPU_CFOH_SUPPORT
-#define F10_DA_CPU_CFOH_SUPPORT
-#define F10_CPU_CFOH_SUPPORT
-#define F15_OR_CPU_CFOH_SUPPORT
-#if OPTION_CPU_CFOH == TRUE
- #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
- #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
- #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
-
- #if OPTION_FAMILY10H_BL == TRUE
- extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
- #undef F10_BL_CPU_CFOH_SUPPORT
- #define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
- #endif
-
- #if OPTION_FAMILY10H_DA == TRUE
- extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
- #undef F10_DA_CPU_CFOH_SUPPORT
- #define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
- #endif
-
- #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
- extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
- #undef F10_CPU_CFOH_SUPPORT
- #define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt},
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
- #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
- #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
-
- #if OPTION_FAMILY15H_OR == TRUE
- extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15CacheFlushOnHalt;
- #undef F15_OR_CPU_CFOH_SUPPORT
- #define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15CacheFlushOnHalt},
- #endif
- #endif
- #endif
- #endif
-#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
{
- F10_BL_CPU_CFOH_SUPPORT
- F10_DA_CPU_CFOH_SUPPORT
- F10_CPU_CFOH_SUPPORT
- F15_OR_CPU_CFOH_SUPPORT
{0, NULL}
};
+
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
{
(sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionCpuCoreLevelingInstall.h
index 43b82c5..dcd5b98 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionCpuCoreLevelingInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionCpuCoreLevelingInstall.h
@@ -53,57 +53,10 @@
* Check to validate the definition
*/
#define OPTION_CPU_CORE_LEVELING_FEAT
-#define F10_REVE_CPU_CORELEVELING_SUPPORT
-#define F10_REVD_CPU_CORELEVELING_SUPPORT
-#define F10_REVC_CPU_CORELEVELING_SUPPORT
-#define F15_CPU_CORELEVELING_SUPPORT
-#if OPTION_CPU_CORELEVLING == TRUE
- #if (AGESA_ENTRY_INIT_EARLY == TRUE)
- // Family 10h
- #if OPTION_FAMILY10H == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
- #undef OPTION_CPU_CORE_LEVELING_FEAT
- #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_FAMILY10H_HY == TRUE
- extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling;
- #undef F10_REVD_CPU_CORELEVELING_SUPPORT
- #define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling},
- #endif
-
- #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE)
- extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling;
- #undef F10_REVC_CPU_CORELEVELING_SUPPORT
- #define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling},
- #endif
-
- #if (OPTION_FAMILY10H_PH == TRUE)
- extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling;
- #undef F10_REVE_CPU_CORELEVELING_SUPPORT
- #define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling},
- #endif
- #endif
- #endif
- // Family 15h
- #if OPTION_FAMILY15H == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
- #undef OPTION_CPU_CORE_LEVELING_FEAT
- #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
-
- extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15CoreLeveling;
- #undef F15_CPU_CORELEVELING_SUPPORT
- #define F15_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15, &F15CoreLeveling},
- #endif
- #endif
-#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
{
- F10_REVE_CPU_CORELEVELING_SUPPORT
- F10_REVD_CPU_CORELEVELING_SUPPORT
- F10_REVC_CPU_CORELEVELING_SUPPORT
- F15_CPU_CORELEVELING_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionDmiInstall.h
index eb4bc91..20600db 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionDmiInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionDmiInstall.h
@@ -71,36 +71,6 @@
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
- // Family 10
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- extern PROC_FAMILY_TABLE ProcFamily10DmiTable;
- #define FAM10_DMI_SUPPORT FAM10_ENABLED,
- #define FAM10_DMI_TABLE &ProcFamily10DmiTable,
- #else
- #define FAM10_DMI_SUPPORT
- #define FAM10_DMI_TABLE
- #endif
- #else
- #define FAM10_DMI_SUPPORT
- #define FAM10_DMI_TABLE
- #endif
-
- // Family 12
- #ifdef OPTION_FAMILY12H
- #if OPTION_FAMILY12H == TRUE
- extern PROC_FAMILY_TABLE ProcFamily12DmiTable;
- #define FAM12_DMI_SUPPORT FAM12_ENABLED,
- #define FAM12_DMI_TABLE &ProcFamily12DmiTable,
- #else
- #define FAM12_DMI_SUPPORT
- #define FAM12_DMI_TABLE
- #endif
- #else
- #define FAM12_DMI_SUPPORT
- #define FAM12_DMI_TABLE
- #endif
-
// Family 14
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
@@ -116,34 +86,13 @@
#define FAM14_DMI_TABLE
#endif
- // Family 15
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- extern PROC_FAMILY_TABLE ProcFamily15DmiTable;
- #define FAM15_DMI_SUPPORT FAM15_ENABLED,
- #define FAM15_DMI_TABLE &ProcFamily15DmiTable,
- #else
- #define FAM15_DMI_SUPPORT
- #define FAM15_DMI_TABLE
- #endif
- #else
- #define FAM15_DMI_SUPPORT
- #define FAM15_DMI_TABLE
- #endif
-
#else
OPTION_DMI_FEATURE GetDmiInfoStub;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
#define USER_DMI_OPTION GetDmiInfoStub
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
- #define FAM10_DMI_SUPPORT
- #define FAM10_DMI_TABLE
- #define FAM12_DMI_SUPPORT
- #define FAM12_DMI_TABLE
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
- #define FAM15_DMI_SUPPORT
- #define FAM15_DMI_TABLE
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
#else
@@ -151,32 +100,20 @@
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
#define USER_DMI_OPTION GetDmiInfoStub
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
- #define FAM10_DMI_SUPPORT
- #define FAM10_DMI_TABLE
- #define FAM12_DMI_SUPPORT
- #define FAM12_DMI_TABLE
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
- #define FAM15_DMI_SUPPORT
- #define FAM15_DMI_TABLE
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
/// DMI supported families enum
typedef enum {
- FAM10_DMI_SUPPORT ///< Conditionally define F10 support
- FAM12_DMI_SUPPORT ///< Conditionally define F12 support
FAM14_DMI_SUPPORT ///< Conditionally define F14 support
- FAM15_DMI_SUPPORT ///< Conditionally define F15 support
NUM_DMI_FAMILIES ///< Number of installed families
} AGESA_DMI_SUPPORTED_FAM;
/* Declare the Family List. An array of pointers to tables that each describe a family */
CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
- FAM10_DMI_TABLE
- FAM12_DMI_TABLE
FAM14_DMI_TABLE
- FAM15_DMI_TABLE
NULL
};
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionGnbInstall.h
index 0b9412f..26acb3f 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionGnbInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionGnbInstall.h
@@ -53,7 +53,7 @@
* Check to validate the definition
*/
-#define GNB_TYPE_LN OPTION_FAMILY12H
+#define GNB_TYPE_LN FALSE
#define GNB_TYPE_ON OPTION_FAMILY14H
#define GNB_TYPE_KR FALSE
#define GNB_TYPE_TN FALSE
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionHtAssistInstall.h
index 175482b..4536b47 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionHtAssistInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionHtAssistInstall.h
@@ -54,41 +54,14 @@
* Check to validate the definition
*/
#define OPTION_HT_ASSIST_FEAT
-#define F10_HT_ASSIST_SUPPORT
-#define F15_HT_ASSIST_SUPPORT
#define HT_ASSIST_AP_DISABLE_CACHE
#define HT_ASSIST_AP_ENABLE_CACHE
#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE)
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_FAMILY10H_HY == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist;
- #undef OPTION_HT_ASSIST_FEAT
- #define OPTION_HT_ASSIST_FEAT &CpuFeatureHtAssist,
- extern CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F10HtAssist;
- #undef F10_HT_ASSIST_SUPPORT
- #define F10_HT_ASSIST_SUPPORT {AMD_FAMILY_10_HY, &F10HtAssist},
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist;
- #undef OPTION_HT_ASSIST_FEAT
- #define OPTION_HT_ASSIST_FEAT &CpuFeatureHtAssist,
- extern CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F15HtAssist;
- #undef F15_HT_ASSIST_SUPPORT
- #define F15_HT_ASSIST_SUPPORT {AMD_FAMILY_15, &F15HtAssist},
- #endif
- #endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtAssistFamilyServiceArray[] =
{
- F10_HT_ASSIST_SUPPORT
- F15_HT_ASSIST_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtAssistFamilyServiceTable =
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionHtInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionHtInstall.h
index a90867d..f561b73 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionHtInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionHtInstall.h
@@ -79,73 +79,25 @@
/*
* Based on user level options, set Ht internal options.
- * For now, Family 10h support will assume single module. For multi module,
* this will have to be changed to not set non-coherent only.
*/
#define OPTION_HT_NON_COHERENT_ONLY FALSE
-#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
/* Fusion Families do not need a non-coherent only option. */
-#else
- // Process Family 10h and 15h by socket, applying the MultiSocket option where it is allowable.
- #if OPTION_G34_SOCKET_SUPPORT == FALSE
- // Hydra has coherent support, other Family 10h should follow MultiSocket support.
- #if OPTION_MULTISOCKET == FALSE
- #undef OPTION_HT_NON_COHERENT_ONLY
- #define OPTION_HT_NON_COHERENT_ONLY TRUE
- #endif
- #endif
-#endif
/*
* Macros will generate the correct item reference based on options
*/
#if AGESA_ENTRY_INIT_EARLY == TRUE
// Select the interface and features
- #if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
+ #if OPTION_FAMILY14H == TRUE
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly
- #else
- // Family 10h and 15h
- #if OPTION_HT_NON_COHERENT_ONLY == FALSE
- #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault
- #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault
- #else
- #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
- #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly
- #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly
- #endif
- #endif
- // Select Northbridge components
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_HT_NON_COHERENT_ONLY == TRUE
- #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly,
- #else
- #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault,
- #endif
- #else
- #define INTERNAL_HT_OPTION_FAM10_NB
- #endif
- #if OPTION_FAMILY12H == TRUE
- #define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb,
- #else
- #define INTERNAL_HT_OPTION_FAM12_NB
- #endif
- #if OPTION_FAMILY14H == TRUE
#define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb,
#else
#define INTERNAL_HT_OPTION_FAM14_NB
#endif
- #if OPTION_FAMILY15H == TRUE
- #if OPTION_HT_NON_COHERENT_ONLY == TRUE
- #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbNonCoherentOnly,
- #else
- #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbDefault,
- #endif
- #else
- #define INTERNAL_HT_OPTION_FAM15_NB
- #endif
#define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
#ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
@@ -158,9 +110,6 @@
*/
#define INTERNAL_HT_OPTION_SUPPORTED_NBS \
INTERNAL_ONLY_NB_LIST_ITEM \
- INTERNAL_HT_OPTION_FAM10_NB \
- INTERNAL_HT_OPTION_FAM15_NB \
- INTERNAL_HT_OPTION_FAM12_NB \
INTERNAL_HT_OPTION_FAM14_NB
#else
@@ -271,18 +220,13 @@
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
- #if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
+ #if OPTION_FAMILY14H == TRUE
#undef OPTION_HT_INIIT_RESET_ENTRY
#undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY NULL
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL
#endif
- #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE))
- #undef OPTION_HT_INIIT_RESET_ENTRY
- #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
- #endif
-
#endif
#ifdef AGESA_ENTRY_INIT_RESET
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionHwC1eInstall.h
index 14058d5..52b15c7 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionHwC1eInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionHwC1eInstall.h
@@ -54,23 +54,9 @@
* Check to validate the definition
*/
#define OPTION_HW_C1E_FEAT
-#define F10_HW_C1E_SUPPORT
#if AGESA_ENTRY_INIT_EARLY == TRUE
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e;
- #undef OPTION_HW_C1E_FEAT
- #define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e,
- extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e;
- #undef F10_HW_C1E_SUPPORT
- #define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e},
- #endif
- #endif
- #endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
{
- F10_HW_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionIdsInstall.h
index 3c68b97..9347eeb 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionIdsInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionIdsInstall.h
@@ -57,10 +57,6 @@
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (IDSOPT_CONTROL_ENABLED == TRUE)
// Check for all families which include HT Features.
- #if (OPTION_FAMILY10H == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)
- #undef M_HTIDS_PORT_OVERRIDE_HOOK
- #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
- #endif
#endif
#endif // OPTION_IDS_LEVEL
CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
@@ -98,90 +94,9 @@
#define OPTION_IDS_EXTEND_FEATS
#endif
- #define OPTION_IDS_FEAT_ECCCTRL\
- OPTION_IDS_FEAT_ECCCTRL_F10 \
- OPTION_IDS_FEAT_ECCCTRL_F12 \
- OPTION_IDS_FEAT_ECCCTRL_F15
-
#define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
- OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \
OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
- #define OPTION_IDS_FEAT_CPB_CTRL\
- OPTION_IDS_FEAT_CPB_CTRL_F12
-
- #define OPTION_IDS_FEAT_HTC_CTRL\
- OPTION_IDS_FEAT_HTC_CTRL_F15
-
- #define OPTION_IDS_FEAT_MEMORY_MAPPING\
- OPTION_IDS_FEAT_MEMORY_MAPPING_F15
-
- #define OPTION_IDS_FEAT_HT_ASSIST\
- OPTION_IDS_FEAT_HT_ASSIST_F10HY \
- OPTION_IDS_FEAT_HT_ASSIST_F15
-
- #define OPTION_IDS_FEAT_ECCSYMBOLSIZE\
- OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \
- OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15
-
-/*----------------------------------------------------------------------------
- * Family 10 feat blocks
- *
- *----------------------------------------------------------------------------
- */
- #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
- #define OPTION_IDS_FEAT_ECCCTRL_F10
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
-//Ecc symbol size
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10;
- #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
- #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10,
-
-//ECC scrub control
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10;
- #undef OPTION_IDS_FEAT_ECCCTRL_F10
- #define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10,
- #endif
- #endif
-
- //Misc Features
- #define OPTION_IDS_FEAT_HT_ASSIST_F10HY
- #ifdef OPTION_FAMILY10H_HY
- #if OPTION_FAMILY10H_HY == TRUE
- #undef OPTION_IDS_FEAT_HT_ASSIST_F10HY
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy;
-
- #define OPTION_IDS_FEAT_HT_ASSIST_F10HY \
- &IdsFeatHtAssistBlockPlatformCfgF10Hy,
- #endif
- #endif
-/*----------------------------------------------------------------------------
- * Family 12 feat blocks
- *
- *----------------------------------------------------------------------------
- */
- #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
- #define OPTION_IDS_FEAT_ECCCTRL_F12
- #define OPTION_IDS_FEAT_CPB_CTRL_F12
- #ifdef OPTION_FAMILY12H
- #if OPTION_FAMILY12H == TRUE
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12;
- #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
- #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12,
-
- //ECC scrub control
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12;
- #undef OPTION_IDS_FEAT_ECCCTRL_F12
- #define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12,
-
- #undef OPTION_IDS_FEAT_CPB_CTRL_F12
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12;
- #define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12,
-
- #endif
- #endif
-
/*----------------------------------------------------------------------------
* Family 14 feat blocks
*
@@ -196,50 +111,6 @@
#endif
#endif
-/*----------------------------------------------------------------------------
- * Family 15 feat blocks
- *
- *----------------------------------------------------------------------------
- */
- #define OPTION_IDS_FEAT_HTC_CTRL_F15
- #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15
- #define OPTION_IDS_FEAT_HT_ASSIST_F15
- #define OPTION_IDS_FEAT_ECCCTRL_F15
- #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15;
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15;
- #undef OPTION_IDS_FEAT_HTC_CTRL_F15
- #define OPTION_IDS_FEAT_HTC_CTRL_F15\
- &IdsFeatHtcControlBlockF15,\
- &IdsFeatHtcControlLateBlockF15,
-
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15;
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15;
- #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15
- #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15\
- &IdsFeatMemoryMappingPostBeforeBlockF15,\
- &IdsFeatMemoryMappingChIntlvBlockF15,
-
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15;
- #undef OPTION_IDS_FEAT_HT_ASSIST_F15
- #define OPTION_IDS_FEAT_HT_ASSIST_F15\
- &IdsFeatHtAssistBlockPlatformCfgF15,
-
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15;
- #undef OPTION_IDS_FEAT_ECCCTRL_F15
- #define OPTION_IDS_FEAT_ECCCTRL_F15 &IdsFeatEccCtrlBlockF15,
-
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15;
- #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15
- #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15 &IdsFeatEccSymbolSizeBlockF15,
-
- #endif
- #endif
-
-
-
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
{
IDS_FEAT_UCODE_UPDATE,
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionIoCstateInstall.h
index bc80a74..25caa82 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionIoCstateInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionIoCstateInstall.h
@@ -55,38 +55,10 @@
*/
#define OPTION_IO_CSTATE_FEAT
-#define F10_IO_CSTATE_SUPPORT
-#define F12_IO_CSTATE_SUPPORT
#define F14_IO_CSTATE_SUPPORT
-#define F15_IO_CSTATE_SUPPORT
#if OPTION_IO_CSTATE == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_FAMILY10H_PH == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
- #undef OPTION_IO_CSTATE_FEAT
- #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
- extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport;
- #undef F10_IO_CSTATE_SUPPORT
- #define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport},
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY12H
- #if OPTION_FAMILY12H == TRUE
- #if OPTION_FAMILY12H_LN == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
- #undef OPTION_IO_CSTATE_FEAT
- #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
- extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport;
- #undef F12_IO_CSTATE_SUPPORT
- #define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport},
- #endif
- #endif
- #endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
@@ -101,28 +73,12 @@
#endif
#endif
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- #if OPTION_FAMILY15H_OR == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
- #undef OPTION_IO_CSTATE_FEAT
- #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
- extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15IoCstateSupport;
- #undef F15_IO_CSTATE_SUPPORT
- #define F15_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15IoCstateSupport},
- #endif
- #endif
- #endif
-
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
{
- F10_IO_CSTATE_SUPPORT
- F12_IO_CSTATE_SUPPORT
F14_IO_CSTATE_SUPPORT
- F15_IO_CSTATE_SUPPORT
{0, NULL}
};
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionLowPwrPstateInstall.h
index 9438abc..ed24658 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionLowPwrPstateInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionLowPwrPstateInstall.h
@@ -54,29 +54,14 @@
* Check to validate the definition
*/
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
-#define F15_LOW_PWR_PSTATE_SUPPORT
#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
- // Family 15h
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- #if OPTION_FAMILY15H_OR == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate;
- #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
- #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate,
- extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15LowPwrPstateSupport;
- #undef F15_LOW_PWR_PSTATE_SUPPORT
- #define F15_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15LowPwrPstateSupport},
- #endif
- #endif
- #endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] =
{
- F15_LOW_PWR_PSTATE_SUPPORT
{0, NULL}
};
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h
index 283a972..98dbd78 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h
@@ -127,149 +127,6 @@
return TRUE;
}
-#if (OPTION_MEMCTLR_DR == TRUE)
- #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
- #if (OPTION_S3_MEM_SUPPORT == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
- #endif
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
- #endif
- #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr;
- #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr
- #else
- #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef
- #endif
-#endif
-
-#if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
- #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
- #if (OPTION_S3_MEM_SUPPORT == TRUE)
- #if (OPTION_MEMCTLR_Ni == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
- #endif
- #if (OPTION_MEMCTLR_DA == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
- #endif
- #if (OPTION_MEMCTLR_PH == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
- #endif
- #if (OPTION_MEMCTLR_RB == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
- #endif
- #endif
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
- #endif
- #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA;
- #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb;
- #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh;
- #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh
- #else
- #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef
- #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef
- #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef
- #endif
-#endif
-
-#if (OPTION_MEMCTLR_OR == TRUE)
- #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
- #if (OPTION_S3_MEM_SUPPORT == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
- #endif
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
- #endif
- #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr;
- #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr
- #else
- #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef
- #endif
-#endif
-
-#if (OPTION_MEMCTLR_HY == TRUE)
- #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
- #if (OPTION_S3_MEM_SUPPORT == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
- #endif
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
- #endif
- #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy;
- #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy
- #else
- #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef
- #endif
-#endif
-
-#if (OPTION_MEMCTLR_C32 == TRUE)
- #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
- #if (OPTION_S3_MEM_SUPPORT == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
- #endif
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
- #endif
- #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32;
- #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32
- #else
- #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef
- #endif
-#endif
-
-#if (OPTION_MEMCTLR_LN == TRUE)
- #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
- #if (OPTION_S3_MEM_SUPPORT == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockLN;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemS3ResumeConstructNBBlockLN
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet
- #endif
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet
- #endif
- #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorLN;
- #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorLN
- #else
- #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorRetDef
- #endif
-#endif
-
#if (OPTION_MEMCTLR_ON == TRUE)
#if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
#if (OPTION_S3_MEM_SUPPORT == TRUE)
@@ -294,15 +151,6 @@
*
*----------------------------------------------------------------------------------
*/
-#define MEM_NB_SUPPORT_DR
-#define MEM_NB_SUPPORT_RB
-#define MEM_NB_SUPPORT_DA
-#define MEM_NB_SUPPORT_Ni
-#define MEM_NB_SUPPORT_PH
-#define MEM_NB_SUPPORT_HY
-#define MEM_NB_SUPPORT_LN
-#define MEM_NB_SUPPORT_OR
-#define MEM_NB_SUPPORT_C32
#define MEM_NB_SUPPORT_ON
#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 }
@@ -315,78 +163,16 @@
*/
extern MEM_FLOW_CFG MemMFlowDef;
- #if (OPTION_MEMCTLR_DR == TRUE)
- extern MEM_FLOW_CFG MemMFlowDr;
- #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr,
- #else
- #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_DA == TRUE)
- extern MEM_FLOW_CFG MemMFlowDA;
- #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA,
- #else
- #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_HY == TRUE)
- extern MEM_FLOW_CFG MemMFlowHy;
- #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy,
- #else
- #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_OR == TRUE)
- extern MEM_FLOW_CFG MemMFlowOr;
- #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr,
- #else
- #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_LN == TRUE)
- extern MEM_FLOW_CFG MemMFlowLN;
- #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN,
- #else
- #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_C32 == TRUE)
- extern MEM_FLOW_CFG MemMFlowC32;
- #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32,
- #else
- #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef,
- #endif
+
#if (OPTION_MEMCTLR_ON == TRUE)
extern MEM_FLOW_CFG MemMFlowON;
#define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON,
#else
#define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef,
#endif
- #if (OPTION_MEMCTLR_Ni == TRUE)
- extern MEM_FLOW_CFG MemMFlowDA;
- #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA,
- #else
- #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_RB == TRUE)
- extern MEM_FLOW_CFG MemMFlowRb;
- #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb,
- #else
- #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_PH == TRUE)
- extern MEM_FLOW_CFG MemMFlowPh;
- #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh,
- #else
- #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef,
- #endif
MEM_FLOW_CFG* memFlowControlInstalled[] = {
- MEM_MAIN_FLOW_CONTROL_PTR_Dr
- MEM_MAIN_FLOW_CONTROL_PTR_DA
- MEM_MAIN_FLOW_CONTROL_PTR_RB
- MEM_MAIN_FLOW_CONTROL_PTR_PH
- MEM_MAIN_FLOW_CONTROL_PTR_Hy
- MEM_MAIN_FLOW_CONTROL_PTR_OR
- MEM_MAIN_FLOW_CONTROL_PTR_LN
- MEM_MAIN_FLOW_CONTROL_PTR_C32
MEM_MAIN_FLOW_CONTROL_PTR_ON
- MEM_MAIN_FLOW_CONTROL_PTR_Ni
NULL
};
@@ -557,355 +343,6 @@
*/
/*---------------------------------------------------------------------------------------------------
- * DEERHOUND FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_DR == TRUE)
- #if OPTION_DDR2
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
- #endif
- #if OPTION_DDR3
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
- #endif
-
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
-
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
- #else
- extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
- #endif
-
- #undef MEM_MAIN_FEATURE_TRAINING
- #undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
- #define MEM_FEATURE_TRAINING MemFStandardTraining
-
- MEM_FEAT_BLOCK_NB MemFeatBlockDr = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MEM_FEATURE_ONLINE_SPARE,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MEM_FEATURE_NODE_INTERLEAVE_CHECK,
- MEM_FEATURE_NODE_INTERLEAVE,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MemFDefRet,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MemFDefRet,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_DR
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR;
- extern MEM_INITIALIZER MemNInitDefaultsDR;
-
-
- #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
- #endif // OPTION_MEMCTRL_DR
-
- /*---------------------------------------------------------------------------------------------------
- * DASHOUND FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
- #if OPTION_DDR2
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
- #endif
- #if OPTION_DDR3
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
- #endif
-
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
-
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
- #else
- extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
- #endif
-
- #undef MEM_MAIN_FEATURE_TRAINING
- #undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
- #define MEM_FEATURE_TRAINING MemFStandardTraining
-
- #if (OPTION_MEMCTLR_Ni == TRUE)
- MEM_FEAT_BLOCK_NB MemFeatBlockNi = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MemFDefRet,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MemFDefRet,
- MemFDefRet,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MEM_FEATURE_REGION_INTERLEAVE,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MemFDefRet,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_Ni
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi;
- extern MEM_INITIALIZER MemNInitDefaultsNi;
-
- #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA },
- #endif
-
- #if (OPTION_MEMCTLR_PH == TRUE)
- MEM_FEAT_BLOCK_NB MemFeatBlockPh = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MemFDefRet,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MemFDefRet,
- MemFDefRet,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MEM_FEATURE_REGION_INTERLEAVE,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MemFDefRet,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_PH
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh;
- extern MEM_INITIALIZER MemNInitDefaultsPh;
-
- #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
- #endif
-
- #if (OPTION_MEMCTLR_RB == TRUE)
- MEM_FEAT_BLOCK_NB MemFeatBlockRb = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MemFDefRet,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MemFDefRet,
- MemFDefRet,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MEM_FEATURE_REGION_INTERLEAVE,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MemFDefRet,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_RB
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb;
- extern MEM_INITIALIZER MemNInitDefaultsRb;
-
- #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
- #endif
-
- #if (OPTION_MEMCTLR_DA == TRUE)
- MEM_FEAT_BLOCK_NB MemFeatBlockDA = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MemFDefRet,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MemFDefRet,
- MemFDefRet,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MEM_FEATURE_REGION_INTERLEAVE,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MemFDefRet,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_DA
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA;
- extern MEM_INITIALIZER MemNInitDefaultsDA;
-
- #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
- #endif
- #endif // OPTION_MEMCTRL_DA
-
- /*---------------------------------------------------------------------------------------------------
- * HYDRA FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_HY == TRUE)
- #if OPTION_DDR2
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
- #endif
- #if OPTION_DDR3
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
- #endif
-
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
-
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
- #else
- extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
- #endif
-
-
- #undef MEM_MAIN_FEATURE_TRAINING
- #undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
- #define MEM_FEATURE_TRAINING MemFStandardTraining
-
- MEM_FEAT_BLOCK_NB MemFeatBlockHy = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MEM_FEATURE_ONLINE_SPARE,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MEM_FEATURE_NODE_INTERLEAVE_CHECK,
- MEM_FEATURE_NODE_INTERLEAVE,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MemFDefRet,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MEM_FEATURE_ONDIMMTHERMAL,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_HY
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY;
- extern MEM_INITIALIZER MemNInitDefaultsHY;
- #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
- #endif // OPTION_MEMCTRL_HY
- /*---------------------------------------------------------------------------------------------------
- * LLANO FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_LN == TRUE)
- #if OPTION_DDR2
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
- #endif
- #if OPTION_DDR3
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
- #endif
-
- #if (OPTION_EARLY_SAMPLES == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportLN;
- #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportLN
- #else
- #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet
- #endif
-
- #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb;
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb
- #else
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
- #endif
-
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
- #else
- extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
- #endif
-
- #undef MEM_MAIN_FEATURE_TRAINING
- #undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
- #define MEM_FEATURE_TRAINING MemFStandardTraining
-
- MEM_FEAT_BLOCK_NB MemFeatBlockLn = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MemFDefRet,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MemFDefRet,
- MemFDefRet,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MEM_FEATURE_REGION_INTERLEAVE,
- MEM_FEATURE_CK_ECC,
- MemFDefRet,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MEM_FEATURE_ONDIMMTHERMAL,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MEM_EARLY_SAMPLE_SUPPORT,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
- #undef MEM_NB_SUPPORT_LN
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockLN;
- extern MEM_INITIALIZER MemNInitDefaultsLN;
- #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockLN, MemNInitDefaultsLN, &MemFeatBlockLn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN },
-
- #endif // OPTION_MEMCTRL_LN
-
- /*---------------------------------------------------------------------------------------------------
* ONTARIO FEATURE BLOCK
*---------------------------------------------------------------------------------------------------
*/
@@ -980,144 +417,6 @@
#endif // OPTION_MEMCTRL_ON
/*---------------------------------------------------------------------------------------------------
- * OROCHI FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_OR == TRUE)
- #if OPTION_DDR2
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
- #endif
- #if OPTION_DDR3
- #undef MEM_MAIN_FEATURE_LVDDR3
- extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre;
- #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
- #endif
-
- #if (OPTION_EARLY_SAMPLES == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr;
- #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportOr
- #else
- #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet
- #endif
-
- #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb;
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemNInitCPGUnb
- #else
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
- #endif
-
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
- #else
- extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
- #endif
-
-
- #undef MEM_MAIN_FEATURE_TRAINING
- #undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
- #define MEM_FEATURE_TRAINING MemFStandardTraining
-
- MEM_FEAT_BLOCK_NB MemFeatBlockOr = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MEM_FEATURE_ONLINE_SPARE,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MEM_FEATURE_NODE_INTERLEAVE_CHECK,
- MEM_FEATURE_NODE_INTERLEAVE,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MemFDefRet,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MEM_FEATURE_ONDIMMTHERMAL,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MEM_EARLY_SAMPLE_SUPPORT,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_OR
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR;
- extern MEM_INITIALIZER MemNInitDefaultsOR;
- #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
- #endif // OPTION_MEMCTRL_OR
-
- /*---------------------------------------------------------------------------------------------------
- * C32 FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_C32 == TRUE)
- #if OPTION_DDR2
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
- #endif
- #if OPTION_DDR3
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
- #endif
-
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
-
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
- #else
- extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
- #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
- #endif
-
- #undef MEM_MAIN_FEATURE_TRAINING
- #undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
- #define MEM_FEATURE_TRAINING MemFStandardTraining
-
- MEM_FEAT_BLOCK_NB MemFeatBlockC32 = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MEM_FEATURE_ONLINE_SPARE,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MEM_FEATURE_NODE_INTERLEAVE_CHECK,
- MEM_FEATURE_NODE_INTERLEAVE,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MemFDefRet,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MEM_FEATURE_ONDIMMTHERMAL,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_C32
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32;
- extern MEM_INITIALIZER MemNInitDefaultsC32;
- #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
- #endif // OPTION_MEMCTRL_C32
-
- /*---------------------------------------------------------------------------------------------------
* MAIN FEATURE BLOCK
*---------------------------------------------------------------------------------------------------
*/
@@ -1143,1052 +442,6 @@
*
*---------------------------------------------------------------------------------------------------
*/
- #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0
- #if OPTION_MEMCTLR_DR
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
- #if OPTION_DDR2
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Dr = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
- #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr },
- #else
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if OPTION_DDR3
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining
- #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #endif
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
- #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Dr = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr },
- #else
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
- #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB)
- #if OPTION_DDR2
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2DA = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2PH = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Rb = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Ni = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
- #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
- #if (OPTION_MEMCTLR_DA)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR2DA },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if (OPTION_MEMCTLR_PH)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if (OPTION_MEMCTLR_RB)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
- #if (OPTION_MEMCTLR_Ni)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if OPTION_DDR3
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining
- #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #endif
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3DA = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ph = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Rb = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ni = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
- #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
- #if (OPTION_MEMCTLR_DA)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if (OPTION_MEMCTLR_PH)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if (OPTION_MEMCTLR_RB)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if (OPTION_MEMCTLR_Ni)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
- #if OPTION_MEMCTLR_HY
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy;
- #if OPTION_DDR2
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Hy = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
- #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy },
- #else
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if OPTION_DDR3
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining
- #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #endif
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
- #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
- #endif
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
- #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
- #endif
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Hy = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
- #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy },
- #else
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
- #if OPTION_MEMCTLR_C32
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32;
- #if OPTION_DDR2
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2C32 = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
- #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 },
- #else
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if OPTION_DDR3
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining
- #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #endif
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
- #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
- #endif
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1
- #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
- #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
- #endif
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3C32 = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
- #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 },
- #else
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
-
- #if OPTION_MEMCTLR_LN
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceLN;
- #if OPTION_DDR3
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3
- #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3LN = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
- #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceLN, &memTechTrainingFeatSequenceDDR3LN },
- #else
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
-
- #if OPTION_MEMCTLR_OR
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr;
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #if OPTION_DDR3
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining
- #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #endif
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
- #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
- #endif
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1
- #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
- #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
- #endif
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3OR = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
- #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR },
- #else
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
#if OPTION_MEMCTLR_ON
extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON;
@@ -2295,31 +548,14 @@
#endif
#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
+
MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32
MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB
MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
};
MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32
MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB
MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
};
/*---------------------------------------------------------------------------------------------------
@@ -2349,349 +585,6 @@
*
*---------------------------------------------------------------------------------------------------
*/
- #if OPTION_MEMCTLR_HY
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUHy3,
- #else
- #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsRHy3,
- #else
- #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsSHy3,
- #else
- #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
- PLAT_SP_HY_FF_UDIMM2
- PLAT_SP_HY_FF_RDIMM2
- PLAT_SP_HY_FF_SDIMM2
- PLAT_SP_HY_FF_UDIMM3
- PLAT_SP_HY_FF_RDIMM3
- PLAT_SP_HY_FF_SDIMM3
- };
-
- #if OPTION_MEMCTLR_DR
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- extern MEM_PLAT_SPEC_CFG MemPConstructPsUDr2;
- #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDr2,
- #else
- #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDr3,
- #else
- #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2;
- #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsRDr2,
- #else
- #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsRDr3,
- #else
- #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsSDr3,
- #else
- #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = {
- PLAT_SP_DR_FF_UDIMM2
- PLAT_SP_DR_FF_RDIMM2
- PLAT_SP_DR_FF_SDIMM2
- PLAT_SP_DR_FF_UDIMM3
- PLAT_SP_DR_FF_RDIMM3
- PLAT_SP_DR_FF_SDIMM3
- };
-
- #if (OPTION_MEMCTLR_DA == TRUE)
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDA3,
- #else
- #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef,
- #else
- #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsSDA2,
- #else
- #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsSDA3,
- #else
- #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
- PLAT_SP_DA_FF_UDIMM2
- PLAT_SP_DA_FF_RDIMM2
- PLAT_SP_DA_FF_SDIMM2
- PLAT_SP_DA_FF_UDIMM3
- PLAT_SP_DA_FF_RDIMM3
- PLAT_SP_DA_FF_SDIMM3
- };
-
- #if (OPTION_MEMCTLR_Ni == TRUE)
- #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsSNi3,
- #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUNi3,
- #else
- #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
- PLAT_SP_NI_FF_UDIMM2
- PLAT_SP_NI_FF_RDIMM2
- PLAT_SP_NI_FF_SDIMM2
- PLAT_SP_NI_FF_UDIMM3
- PLAT_SP_NI_FF_RDIMM3
- PLAT_SP_NI_FF_SDIMM3
- };
-
- #if (OPTION_MEMCTLR_PH == TRUE)
- #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsSPh3,
- #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUPh3,
- #else
- #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
- PLAT_SP_PH_FF_UDIMM2
- PLAT_SP_PH_FF_RDIMM2
- PLAT_SP_PH_FF_SDIMM2
- PLAT_SP_PH_FF_UDIMM3
- PLAT_SP_PH_FF_RDIMM3
- PLAT_SP_PH_FF_SDIMM3
- };
-
- #if (OPTION_MEMCTLR_RB == TRUE)
- #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsSRb3,
- #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsURb3,
- #else
- #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
- PLAT_SP_RB_FF_UDIMM2
- PLAT_SP_RB_FF_RDIMM2
- PLAT_SP_RB_FF_SDIMM2
- PLAT_SP_RB_FF_UDIMM3
- PLAT_SP_RB_FF_RDIMM3
- PLAT_SP_RB_FF_SDIMM3
- };
-
- #if OPTION_MEMCTLR_LN
- #if OPTION_UDIMMS
- #if OPTION_DDR3
- #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsULN3,
- #else
- #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR3
- #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsSLN3,
- #else
- #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[] = {
- PLAT_SP_LN_FF_SDIMM3
- PLAT_SP_LN_FF_UDIMM3
- NULL
- };
-
- #if OPTION_MEMCTLR_C32
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUC32_3,
- #else
- #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsRC32_3,
- #else
- #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_SODIMMS
- #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
- PLAT_SP_C32_FF_UDIMM2
- PLAT_SP_C32_FF_RDIMM2
- PLAT_SP_C32_FF_SDIMM2
- PLAT_SP_C32_FF_UDIMM3
- PLAT_SP_C32_FF_RDIMM3
- PLAT_SP_C32_FF_SDIMM3
- };
#if OPTION_MEMCTLR_ON
#if OPTION_UDIMMS
@@ -2729,266 +622,6 @@
*---------------------------------------------------------------------------------------------------
*/
- #if OPTION_MEMCTLR_DR
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PSC_DR_UDIMM_DDR2 //MemAGetPsCfgUDr2
- #else
- #define PSC_DR_UDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_DR_UDIMM_DDR3 MemAGetPsCfgUDr3,
- #else
- #define PSC_DR_UDIMM_DDR3
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PSC_DR_RDIMM_DDR2 MemAGetPsCfgRDr2,
- #else
- #define PSC_DR_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_DR_RDIMM_DDR3 MemAGetPsCfgRDr3,
- #else
- #define PSC_DR_RDIMM_DDR3
- #endif
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PSC_DR_SODIMM_DDR2 //MemAGetPsCfgSDr2
- #else
- #define PSC_DR_SODIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_DR_SODIMM_DDR3 //MemAGetPsCfgSDr3
- #else
- #define PSC_DR_SODIMM_DDR3
- #endif
- #endif
- #endif
-
- #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
- #if OPTION_MEMCTLR_Ni
- #define PSC_NI_UDIMM_DDR2
- #define PSC_NI_UDIMM_DDR3 MemAGetPsCfgUNi3,
- #define PSC_NI_RDIMM_DDR2
- #define PSC_NI_RDIMM_DDR3
- #define PSC_NI_SODIMM_DDR2
- #define PSC_NI_SODIMM_DDR3 MemAGetPsCfgSNi3,
- #endif
- #if OPTION_MEMCTLR_PH
- #define PSC_PH_UDIMM_DDR2
- #define PSC_PH_UDIMM_DDR3 MemAGetPsCfgUPh3,
- #define PSC_PH_RDIMM_DDR2
- #define PSC_PH_RDIMM_DDR3
- #define PSC_PH_SODIMM_DDR2
- #define PSC_PH_SODIMM_DDR3 MemAGetPsCfgSPh3,
- #endif
- #if OPTION_MEMCTLR_RB
- #define PSC_RB_UDIMM_DDR2
- #define PSC_RB_UDIMM_DDR3 MemAGetPsCfgURb3,
- #define PSC_RB_RDIMM_DDR2
- #define PSC_RB_RDIMM_DDR3
- #define PSC_RB_SODIMM_DDR2
- #define PSC_RB_SODIMM_DDR3 MemAGetPsCfgSRb3,
- #endif
- #if OPTION_MEMCTLR_DA
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PSC_DA_UDIMM_DDR2 //MemAGetPsCfgUDr2
- #else
- #define PSC_DA_UDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_DA_UDIMM_DDR3 MemAGetPsCfgUDA3,
- #else
- #define PSC_DA_UDIMM_DDR3
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PSC_DA_RDIMM_DDR2
- #else
- #define PSC_DA_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_DA_RDIMM_DDR3
- #else
- #define PSC_DA_RDIMM_DDR3
- #endif
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PSC_DA_SODIMM_DDR2 MemAGetPsCfgSDA2,
- #else
- #define PSC_DA_SODIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_DA_SODIMM_DDR3 MemAGetPsCfgSDA3,
- #else
- #define PSC_DA_SODIMM_DDR3
- #endif
- #endif
- #endif
- #endif
-
- #if OPTION_MEMCTLR_HY
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PSC_HY_UDIMM_DDR2 //MemAGetPsCfgUDr2,
- #else
- #define PSC_HY_UDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_HY_UDIMM_DDR3 MemAGetPsCfgUHy3,
- #else
- #define PSC_HY_UDIMM_DDR3
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PSC_HY_RDIMM_DDR2
- #else
- #define PSC_HY_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_HY_RDIMM_DDR3 MemAGetPsCfgRHy3,
- #else
- #define PSC_HY_RDIMM_DDR3
- #endif
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PSC_HY_SODIMM_DDR2 //MemAGetPsCfgSHy2,
- #else
- #define PSC_HY_SODIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_HY_SODIMM_DDR3 //MemAGetPsCfgSHy3,
- #else
- #define PSC_HY_SODIMM_DDR3
- #endif
- #endif
- #endif
-
- #if OPTION_MEMCTLR_C32
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PSC_C32_UDIMM_DDR2 //MemAGetPsCfgUDr2,
- #else
- #define PSC_C32_UDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_C32_UDIMM_DDR3 MemAGetPsCfgUC32_3,
- #else
- #define PSC_C32_UDIMM_DDR3
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PSC_C32_RDIMM_DDR2
- #else
- #define PSC_C32_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_C32_RDIMM_DDR3 MemAGetPsCfgRC32_3,
- #else
- #define PSC_C32_RDIMM_DDR3
- #endif
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PSC_C32_SODIMM_DDR2 //MemAGetPsCfgSC32_2,
- #else
- #define PSC_C32_SODIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_C32_SODIMM_DDR3 //MemAGetPsCfgSC32_3,
- #else
- #define PSC_C32_SODIMM_DDR3
- #endif
- #endif
- #endif
-
- #if OPTION_MEMCTLR_LN
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PSC_LN_UDIMM_DDR2 //MemAGetPsCfgULN2,
- #else
- #define PSC_LN_UDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_LN_UDIMM_DDR3 MemAGetPsCfgULN3,
- #else
- #define PSC_LN_UDIMM_DDR3
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PSC_LN_RDIMM_DDR2
- #else
- #define PSC_LN_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_LN_RDIMM_DDR3 //MemAGetPsCfgRLN3,
- #else
- #define PSC_LN_RDIMM_DDR3
- #endif
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PSC_LN_SODIMM_DDR2 //MemAGetPsCfgSLN2,
- #else
- #define PSC_LN_SODIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_LN_SODIMM_DDR3 MemAGetPsCfgSLN3,
- #else
- #define PSC_LN_SODIMM_DDR3
- #endif
- #endif
- #endif
-
- #if OPTION_MEMCTLR_OR
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PSC_OR_UDIMM_DDR2 //MemAGetPsCfgUOr2,
- #else
- #define PSC_OR_UDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_OR_UDIMM_DDR3 //MemAGetPsCfgUOr3,
- #else
- #define PSC_OR_UDIMM_DDR3
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PSC_OR_RDIMM_DDR2
- #else
- #define PSC_OR_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_OR_RDIMM_DDR3 //MemAGetPsCfgROr3,
- #else
- #define PSC_OR_RDIMM_DDR3
- #endif
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PSC_OR_SODIMM_DDR2 //MemAGetPsCfgSOr2,
- #else
- #define PSC_OR_SODIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_OR_SODIMM_DDR3 //MemAGetPsCfgSOr3,
- #else
- #define PSC_OR_SODIMM_DDR3
- #endif
- #endif
- #endif
-
#if OPTION_MEMCTLR_ON
#if OPTION_UDIMMS
#if OPTION_DDR2
@@ -3034,165 +667,6 @@
*----------------------------------------------------------------------
*/
- #ifndef PSC_DR_UDIMM_DDR2
- #define PSC_DR_UDIMM_DDR2
- #endif
- #ifndef PSC_DR_RDIMM_DDR2
- #define PSC_DR_RDIMM_DDR2
- #endif
- #ifndef PSC_DR_SODIMM_DDR2
- #define PSC_DR_SODIMM_DDR2
- #endif
- #ifndef PSC_DR_UDIMM_DDR3
- #define PSC_DR_UDIMM_DDR3
- #endif
- #ifndef PSC_DR_RDIMM_DDR3
- #define PSC_DR_RDIMM_DDR3
- #endif
- #ifndef PSC_DR_SODIMM_DDR3
- #define PSC_DR_SODIMM_DDR3
- #endif
- #ifndef PSC_RB_UDIMM_DDR2
- #define PSC_RB_UDIMM_DDR2
- #endif
- #ifndef PSC_RB_RDIMM_DDR2
- #define PSC_RB_RDIMM_DDR2
- #endif
- #ifndef PSC_RB_SODIMM_DDR2
- #define PSC_RB_SODIMM_DDR2
- #endif
- #ifndef PSC_RB_UDIMM_DDR3
- #define PSC_RB_UDIMM_DDR3
- #endif
- #ifndef PSC_RB_RDIMM_DDR3
- #define PSC_RB_RDIMM_DDR3
- #endif
- #ifndef PSC_RB_SODIMM_DDR3
- #define PSC_RB_SODIMM_DDR3
- #endif
- #ifndef PSC_DA_UDIMM_DDR2
- #define PSC_DA_UDIMM_DDR2
- #endif
- #ifndef PSC_DA_RDIMM_DDR2
- #define PSC_DA_RDIMM_DDR2
- #endif
- #ifndef PSC_DA_SODIMM_DDR2
- #define PSC_DA_SODIMM_DDR2
- #endif
- #ifndef PSC_DA_UDIMM_DDR3
- #define PSC_DA_UDIMM_DDR3
- #endif
- #ifndef PSC_DA_RDIMM_DDR3
- #define PSC_DA_RDIMM_DDR3
- #endif
- #ifndef PSC_DA_SODIMM_DDR3
- #define PSC_DA_SODIMM_DDR3
- #endif
- #ifndef PSC_NI_UDIMM_DDR2
- #define PSC_NI_UDIMM_DDR2
- #endif
- #ifndef PSC_NI_RDIMM_DDR2
- #define PSC_NI_RDIMM_DDR2
- #endif
- #ifndef PSC_NI_SODIMM_DDR2
- #define PSC_NI_SODIMM_DDR2
- #endif
- #ifndef PSC_NI_UDIMM_DDR3
- #define PSC_NI_UDIMM_DDR3
- #endif
- #ifndef PSC_NI_RDIMM_DDR3
- #define PSC_NI_RDIMM_DDR3
- #endif
- #ifndef PSC_NI_SODIMM_DDR3
- #define PSC_NI_SODIMM_DDR3
- #endif
- #ifndef PSC_PH_UDIMM_DDR2
- #define PSC_PH_UDIMM_DDR2
- #endif
- #ifndef PSC_PH_RDIMM_DDR2
- #define PSC_PH_RDIMM_DDR2
- #endif
- #ifndef PSC_PH_SODIMM_DDR2
- #define PSC_PH_SODIMM_DDR2
- #endif
- #ifndef PSC_PH_UDIMM_DDR3
- #define PSC_PH_UDIMM_DDR3
- #endif
- #ifndef PSC_PH_RDIMM_DDR3
- #define PSC_PH_RDIMM_DDR3
- #endif
- #ifndef PSC_PH_SODIMM_DDR3
- #define PSC_PH_SODIMM_DDR3
- #endif
- #ifndef PSC_HY_UDIMM_DDR2
- #define PSC_HY_UDIMM_DDR2
- #endif
- #ifndef PSC_HY_RDIMM_DDR2
- #define PSC_HY_RDIMM_DDR2
- #endif
- #ifndef PSC_HY_SODIMM_DDR2
- #define PSC_HY_SODIMM_DDR2
- #endif
- #ifndef PSC_HY_UDIMM_DDR3
- #define PSC_HY_UDIMM_DDR3
- #endif
- #ifndef PSC_HY_RDIMM_DDR3
- #define PSC_HY_RDIMM_DDR3
- #endif
- #ifndef PSC_HY_SODIMM_DDR3
- #define PSC_HY_SODIMM_DDR3
- #endif
- #ifndef PSC_LN_UDIMM_DDR2
- #define PSC_LN_UDIMM_DDR2
- #endif
- #ifndef PSC_LN_RDIMM_DDR2
- #define PSC_LN_RDIMM_DDR2
- #endif
- #ifndef PSC_LN_SODIMM_DDR2
- #define PSC_LN_SODIMM_DDR2
- #endif
- #ifndef PSC_LN_UDIMM_DDR3
- #define PSC_LN_UDIMM_DDR3
- #endif
- #ifndef PSC_LN_RDIMM_DDR3
- #define PSC_LN_RDIMM_DDR3
- #endif
- #ifndef PSC_LN_SODIMM_DDR3
- #define PSC_LN_SODIMM_DDR3
- #endif
- #ifndef PSC_OR_UDIMM_DDR2
- #define PSC_OR_UDIMM_DDR2
- #endif
- #ifndef PSC_OR_RDIMM_DDR2
- #define PSC_OR_RDIMM_DDR2
- #endif
- #ifndef PSC_OR_SODIMM_DDR2
- #define PSC_OR_SODIMM_DDR2
- #endif
- #ifndef PSC_OR_UDIMM_DDR3
- #define PSC_OR_UDIMM_DDR3
- #endif
- #ifndef PSC_OR_RDIMM_DDR3
- #define PSC_OR_RDIMM_DDR3
- #endif
- #ifndef PSC_OR_SODIMM_DDR3
- #define PSC_OR_SODIMM_DDR3
- #endif
- #ifndef PSC_C32_UDIMM_DDR3
- #define PSC_C32_UDIMM_DDR3
- #endif
- #ifndef PSC_C32_RDIMM_DDR3
- #define PSC_C32_RDIMM_DDR3
- #endif
- #ifndef PSC_ON_UDIMM_DDR2
- #define PSC_ON_UDIMM_DDR2
- #endif
- #ifndef PSC_ON_RDIMM_DDR2
- #define PSC_ON_RDIMM_DDR2
- #endif
- #ifndef PSC_ON_SODIMM_DDR2
- #define PSC_ON_SODIMM_DDR2
- #endif
#ifndef PSC_ON_UDIMM_DDR3
#define PSC_ON_UDIMM_DDR3
#endif
@@ -3204,32 +678,6 @@
#endif
MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
- PSC_DR_UDIMM_DDR2
- PSC_DR_RDIMM_DDR2
- PSC_DR_SODIMM_DDR2
- PSC_DR_UDIMM_DDR3
- PSC_DR_RDIMM_DDR3
- PSC_DR_SODIMM_DDR3
- PSC_RB_UDIMM_DDR3
- PSC_RB_SODIMM_DDR3
- PSC_DA_SODIMM_DDR2
- PSC_DA_UDIMM_DDR3
- PSC_DA_SODIMM_DDR3
- PSC_NI_UDIMM_DDR3
- PSC_NI_SODIMM_DDR3
- PSC_PH_UDIMM_DDR3
- PSC_PH_SODIMM_DDR3
- PSC_HY_UDIMM_DDR3
- PSC_HY_RDIMM_DDR3
- PSC_HY_SODIMM_DDR3
- PSC_LN_UDIMM_DDR3
- PSC_LN_RDIMM_DDR3
- PSC_LN_SODIMM_DDR3
- PSC_OR_UDIMM_DDR3
- PSC_OR_RDIMM_DDR3
- PSC_OR_SODIMM_DDR3
- PSC_C32_UDIMM_DDR3
- PSC_C32_RDIMM_DDR3
PSC_ON_UDIMM_DDR3
PSC_ON_RDIMM_DDR3
PSC_ON_SODIMM_DDR3
@@ -3250,556 +698,8 @@
#define PSC_TBL_END NULL
#define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
- #if OPTION_MEMCTLR_OR
- #if OPTION_UDIMMS
- #if OPTION_AM3_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY MaxFreqTblEntUAM3;
- #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 &MaxFreqTblEntUAM3,
- extern PSC_TBL_ENTRY DramTermTblEntUAM3;
- #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &DramTermTblEntUAM3,
- extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &OdtPat1DTblEntUAM3,
- extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 &OdtPat2DTblEntUAM3,
- extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &OdtPat3DTblEntUAM3,
- extern PSC_TBL_ENTRY SAOTblEntUAM3;
- #define PSC_TBL_OR_UDIMM3_SAO_AM3 &SAOTblEntUAM3,
- extern PSC_TBL_ENTRY ClkDisMapEntUAM3;
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3,
- #endif
- #if OPTION_C32_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY MaxFreqTblEntUC32;
- #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 &MaxFreqTblEntUC32,
- extern PSC_TBL_ENTRY DramTermTblEntUC32;
- #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 &DramTermTblEntUC32,
- extern PSC_TBL_ENTRY OdtPat1DTblEntUC32;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntUC32,
- extern PSC_TBL_ENTRY OdtPat2DTblEntUC32;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntUC32,
- extern PSC_TBL_ENTRY OdtPat3DTblEntUC32;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntUC32,
- extern PSC_TBL_ENTRY SAOTblEntUC32;
- #define PSC_TBL_OR_UDIMM3_SAO_C32 &SAOTblEntUC32,
- extern PSC_TBL_ENTRY ClkDisMapEntUC32;
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32,
- extern PSC_TBL_ENTRY ClkDisMap3DEntUC32;
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32,
- #endif
- #if OPTION_G34_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY MaxFreqTblEntUG34;
- #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 &MaxFreqTblEntUG34,
- extern PSC_TBL_ENTRY DramTermTblEntUG34;
- #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 &DramTermTblEntUG34,
- extern PSC_TBL_ENTRY OdtPat1DTblEntUG34;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntUG34,
- extern PSC_TBL_ENTRY OdtPat2DTblEntUG34;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntUG34,
- extern PSC_TBL_ENTRY OdtPat3DTblEntUG34;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntUG34,
- extern PSC_TBL_ENTRY SAOTblEntUG34;
- #define PSC_TBL_OR_UDIMM3_SAO_G34 &SAOTblEntUG34,
- extern PSC_TBL_ENTRY ClkDisMapEntUG34;
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34,
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_C32_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY MaxFreqTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 &MaxFreqTblEntRC32,
- extern PSC_TBL_ENTRY DramTermTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 &DramTermTblEntRC32,
- extern PSC_TBL_ENTRY OdtPat1DTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntRC32,
- extern PSC_TBL_ENTRY OdtPat2DTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntRC32,
- extern PSC_TBL_ENTRY OdtPat3DTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntRC32,
- extern PSC_TBL_ENTRY SAOTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_SAO_C32 &SAOTblEntRC32,
- extern PSC_TBL_ENTRY RC2IBTTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 &RC2IBTTblEntRC32,
- extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 &RC10OpSpdTblEntRC32,
- extern PSC_TBL_ENTRY ClkDisMapEntRC32;
- #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32,
- #endif
- #if OPTION_G34_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY MaxFreqTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 &MaxFreqTblEntRG34,
- extern PSC_TBL_ENTRY DramTermTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 &DramTermTblEntRG34,
- extern PSC_TBL_ENTRY OdtPat1DTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntRG34,
- extern PSC_TBL_ENTRY OdtPat2DTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntRG34,
- extern PSC_TBL_ENTRY OdtPat3DTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntRG34,
- extern PSC_TBL_ENTRY SAOTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_SAO_G34 &SAOTblEntRG34,
- extern PSC_TBL_ENTRY RC2IBTTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 &RC2IBTTblEntRG34,
- extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 &RC10OpSpdTblEntRG34,
- extern PSC_TBL_ENTRY ClkDisMapEntRG34;
- #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34,
- #endif
- #endif
- //#if OPTION_SODIMMS
- //#endif
- //#if OPTION_LRDIMMS
- // #if OPTION_C32_SOCKET_SUPPORT
- // extern PSC_TBL_ENTRY MaxFreqTblEntLRC32;
- // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 &MaxFreqTblEntLRC32,
- // extern PSC_TBL_ENTRY DramTermTblEntLRC32;
- // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 &DramTermTblEntLRC32,
- // extern PSC_TBL_ENTRY OdtPat1DTblEntRC32;
- // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntLRC32,
- // extern PSC_TBL_ENTRY OdtPat2DTblEntRC32;
- // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntLRC32,
- // extern PSC_TBL_ENTRY OdtPat3DTblEntRC32;
- // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntLRC32,
- // extern PSC_TBL_ENTRY SAOTblEntRC32;
- // #define PSC_TBL_OR_LRDIMM3_SAO_C32 &SAOTblEntLRC32,
- // extern PSC_TBL_ENTRY IBTTblEntLRC32;
- // #define PSC_TBL_OR_LRDIMM3_IBT_C32 &IBTTblEntLRC32,
- // extern PSC_TBL_ENTRY ClkDisMapEntLRC32;
- // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32,
- // #endif
- // #if OPTION_G34_SOCKET_SUPPORT
- // extern PSC_TBL_ENTRY MaxFreqTblEntLRG34;
- // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 &MaxFreqTblEntLRG34,
- // extern PSC_TBL_ENTRY DramTermTblEntLRG34;
- // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 &DramTermTblEntLRG34,
- // extern PSC_TBL_ENTRY OdtPat1DTblEntRG34;
- // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntLRG34,
- // extern PSC_TBL_ENTRY OdtPat2DTblEntRG34;
- // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntLRG34,
- // extern PSC_TBL_ENTRY OdtPat3DTblEntRG34;
- // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntLRG34,
- // extern PSC_TBL_ENTRY SAOTblEntRG34;
- // #define PSC_TBL_OR_LRDIMM3_SAO_G34 &SAOTblEntLRG34,
- // extern PSC_TBL_ENTRY IBTTblEntLRG34;
- // #define PSC_TBL_OR_LRDIMM3_IBT_G34 &IBTTblEntLRG34,
- // extern PSC_TBL_ENTRY ClkDisMapEntLRG34;
- // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34,
- // #endif
- //#endif
- extern PSC_TBL_ENTRY MR0WrTblEntry;
- #define PSC_TBL_OR_MR0_WR &MR0WrTblEntry,
- extern PSC_TBL_ENTRY MR0CLTblEntry;
- #define PSC_TBL_OR_MR0_CL &MR0CLTblEntry,
- extern PSC_TBL_ENTRY OrDdr3CKETriEnt;
- #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt,
- extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt;
- #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt,
- extern PSC_TBL_ENTRY OrDdr3ODTTriEnt;
- #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt,
- extern PSC_TBL_ENTRY OrUDdr3CSTriEnt;
- #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt,
- extern PSC_TBL_ENTRY OrDdr3CSTriEnt;
- #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt,
- extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt;
- #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt,
- extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt;
- #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt,
-
- #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
- #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
- #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
- #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
- #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
- #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
- #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3
- #define PSC_TBL_OR_UDIMM3_SAO_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_SAO_C32
- #define PSC_TBL_OR_UDIMM3_SAO_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_SAO_G34
- #define PSC_TBL_OR_UDIMM3_SAO_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
- #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
- #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
- #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
- #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
- #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
- #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3
- #define PSC_TBL_OR_RDIMM3_SAO_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_SAO_C32
- #define PSC_TBL_OR_RDIMM3_SAO_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_SAO_G34
- #define PSC_TBL_OR_RDIMM3_SAO_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3
- #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32
- #define PSC_TBL_OR_RDIMM3_RC2IBT_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34
- #define PSC_TBL_OR_RDIMM3_RC2IBT_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
- #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
- #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
- #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
- #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
- #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
- #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
- #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
- #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
- #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
- #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
- #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
- #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
- #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32
- #define PSC_TBL_OR_LRDIMM3_SAO_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34
- #define PSC_TBL_OR_LRDIMM3_SAO_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32
- #define PSC_TBL_OR_LRDIMM3_IBT_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34
- #define PSC_TBL_OR_LRDIMM3_IBT_G34
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32
- #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34
- #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
- #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
- #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
- #endif
-
- PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = {
- PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
- PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
- PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
- PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
- PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
- PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
- PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
- PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = {
- PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
- PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
- PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
- PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
- PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
- PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
- PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
- PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = {
- PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
- PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
- PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
- PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
- PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
- PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
- PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
- PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
- PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
- PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
- PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
- PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
- PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
- PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
- PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
- PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
- PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
- PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
- PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
- PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
- PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
- PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
- PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
- PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = {
- PSC_TBL_OR_UDIMM3_SAO_AM3
- PSC_TBL_OR_UDIMM3_SAO_C32
- PSC_TBL_OR_UDIMM3_SAO_G34
- PSC_TBL_OR_RDIMM3_SAO_AM3
- PSC_TBL_OR_RDIMM3_SAO_C32
- PSC_TBL_OR_RDIMM3_SAO_G34
- PSC_TBL_OR_LRDIMM3_SAO_C32
- PSC_TBL_OR_LRDIMM3_SAO_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = {
- PSC_TBL_OR_MR0_WR
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = {
- PSC_TBL_OR_MR0_CL
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = {
- PSC_TBL_OR_RDIMM3_RC2IBT_AM3
- PSC_TBL_OR_RDIMM3_RC2IBT_C32
- PSC_TBL_OR_RDIMM3_RC2IBT_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = {
- PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
- PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
- PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = {
- PSC_TBL_OR_LRDIMM3_IBT_C32
- PSC_TBL_OR_LRDIMM3_IBT_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = {
- PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
- PSC_TBL_OR_UDIMM3_CLK_DIS_C32
- PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
- PSC_TBL_OR_UDIMM3_CLK_DIS_G34
- PSC_TBL_OR_RDIMM3_CLK_DIS_C32
- PSC_TBL_OR_RDIMM3_CLK_DIS_G34
- PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
- PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
- PSC_TBL_OR_CKE_TRI
- PSC_TBL_OR_ODT_TRI_3D
- PSC_TBL_OR_ODT_TRI
- PSC_TBL_OR_LRDIMM3_ODT_TRI_3D
- PSC_TBL_OR_LRDIMM3_ODT_TRI
- PSC_TBL_OR_UDIMM3_CS_TRI
- PSC_TBL_OR_CS_TRI
- PSC_TBL_END
- };
-
- MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = {
- (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR,
- NULL,
- NULL,
- (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR
- };
-
- extern MEM_PSC_FLOW MemPGetMaxFreqSupported;
- #define PSC_FLOW_OR_MAX_FREQ MemPGetMaxFreqSupported
- extern MEM_PSC_FLOW MemPGetRttNomWr;
- #define PSC_FLOW_OR_DRAM_TERM MemPGetRttNomWr
- extern MEM_PSC_FLOW MemPGetODTPattern;
- #define PSC_FLOW_OR_ODT_PATTERN MemPGetODTPattern
- extern MEM_PSC_FLOW MemPGetSAO;
- #define PSC_FLOW_OR_SAO MemPGetSAO
- extern MEM_PSC_FLOW MemPGetMR0WrCL;
- #define PSC_FLOW_OR_MR0_WRCL MemPGetMR0WrCL
- #if OPTION_RDIMMS
- extern MEM_PSC_FLOW MemPGetRC2IBT;
- #define PSC_FLOW_OR_RC2_IBT MemPGetRC2IBT
- extern MEM_PSC_FLOW MemPGetRC10OpSpd;
- #define PSC_FLOW_OR_RC10_OPSPD MemPGetRC10OpSpd
- #endif
- //#if OPTION_LRDIMMS
- //extern MEM_PSC_FLOW MemPGetLRIBT;
- //#define PSC_FLOW_OR_LR_IBT MemPGetLRIBT
- //extern MEM_PSC_FLOW MemPGetLRNPR;
- //#define PSC_FLOW_OR_LR_NPR MemPGetLRNPR
- //extern MEM_PSC_FLOW MemPGetLRNLR;
- //#define PSC_FLOW_OR_LR_NLR MemPGetLRNLR
- //#endif
- #ifndef PSC_FLOW_OR_MAX_FREQ
- #define PSC_FLOW_OR_MAX_FREQ MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_DRAM_TERM
- #define PSC_FLOW_OR_DRAM_TERM MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_ODT_PATTERN
- #define PSC_FLOW_OR_ODT_PATTERN MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_SAO
- #define PSC_FLOW_OR_SAO MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_MR0_WRCL
- #define PSC_FLOW_OR_MR0_WRCL MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_RC2_IBT
- #define PSC_FLOW_OR_RC2_IBT MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_RC10_OPSPD
- #define PSC_FLOW_OR_RC10_OPSPD MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_LR_IBT
- #define PSC_FLOW_OR_LR_IBT MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_LR_NPR
- #define PSC_FLOW_OR_LR_NPR MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_LR_NLR
- #define PSC_FLOW_OR_LR_NLR MEM_PSC_FLOW_DEFTRUE
- #endif
- MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = {
- &memPSCTblBlockOr,
- PSC_FLOW_OR_MAX_FREQ,
- PSC_FLOW_OR_DRAM_TERM,
- PSC_FLOW_OR_ODT_PATTERN,
- PSC_FLOW_OR_SAO,
- PSC_FLOW_OR_MR0_WRCL,
- PSC_FLOW_OR_RC2_IBT,
- PSC_FLOW_OR_RC10_OPSPD,
- PSC_FLOW_OR_LR_IBT,
- PSC_FLOW_OR_LR_NPR,
- PSC_FLOW_OR_LR_NLR
- };
- #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR,
- #else
- #define MEM_PSC_FLOW_BLOCK_OR
- #endif
-
MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
- MEM_PSC_FLOW_BLOCK_OR
MEM_PSC_FLOW_BLOCK_END
};
@@ -3810,12 +710,7 @@
*---------------------------------------------------------------------------------------------------
*/
#if (OPTION_LRDIMMS == TRUE)
- #if (OPTION_MEMCTLR_OR == TRUE)
- extern MEM_TECH_FEAT MemTLrdimmConstructor3;
- #define MEM_TECH_FEATURE_LRDIMM_INIT &MemTLrdimmConstructor3
- #else //#if (OPTION_MEMCTLR_OR == FALSE)
- #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef
- #endif
+ #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef
#else //#if (OPTION_LRDIMMS == FALSE)
#define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef
#endif
@@ -3874,42 +769,11 @@
*
*---------------------------------------------------------------------------------------------------
*/
- #if (OPTION_MEMCTLR_DR == TRUE)
- #undef MEM_NB_SUPPORT_DR
- #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
- #endif
- #if (OPTION_MEMCTLR_RB == TRUE)
- #undef MEM_NB_SUPPORT_RB
- #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
- #endif
- #if (OPTION_MEMCTLR_DA == TRUE)
- #undef MEM_NB_SUPPORT_DA
- #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
- #endif
- #if (OPTION_MEMCTLR_PH == TRUE)
- #undef MEM_NB_SUPPORT_PH
- #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
- #endif
- #if (OPTION_MEMCTLR_HY == TRUE)
- #undef MEM_NB_SUPPORT_HY
- #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
- #endif
- #if (OPTION_MEMCTLR_C32 == TRUE)
- #undef MEM_NB_SUPPORT_C32
- #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
- #endif
- #if (OPTION_MEMCTLR_LN == TRUE)
- #undef MEM_NB_SUPPORT_LN
- #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN },
- #endif
#if (OPTION_MEMCTLR_ON == TRUE)
#undef MEM_NB_SUPPORT_ON
#define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
#endif
- #if (OPTION_MEMCTLR_OR == TRUE)
- #undef MEM_NB_SUPPORT_OR
- #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
- #endif
+
/*---------------------------------------------------------------------------------------------------
* DEFAULT Technology Training
*
@@ -3932,57 +796,13 @@
{ 0 }
};
#endif
+
/*---------------------------------------------------------------------------------------------------
* DEFAULT Platform Specific list
*
*
*---------------------------------------------------------------------------------------------------
*/
- #if (OPTION_MEMCTLR_DR == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_RB == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_DA == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_Ni == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_PH == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_LN == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_HY == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_OR == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_C32 == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
- NULL
- };
- #endif
#if (OPTION_MEMCTLR_ON == TRUE)
MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = {
NULL
@@ -4019,14 +839,6 @@
*---------------------------------------------------------------------------------------------------
*/
MEM_NB_SUPPORT memNBInstalled[] = {
- MEM_NB_SUPPORT_RB
- MEM_NB_SUPPORT_DA
- MEM_NB_SUPPORT_Ni
- MEM_NB_SUPPORT_PH
- MEM_NB_SUPPORT_HY
- MEM_NB_SUPPORT_LN
- MEM_NB_SUPPORT_OR
- MEM_NB_SUPPORT_C32
MEM_NB_SUPPORT_ON
MEM_NB_SUPPORT_END
};
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionMsgBasedC1eInstall.h
index 49c746a..3f9646c 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionMsgBasedC1eInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionMsgBasedC1eInstall.h
@@ -54,59 +54,11 @@
* Check to validate the definition
*/
#define OPTION_MSG_BASED_C1E_FEAT
-#define F10_MSG_BASED_C1E_SUPPORT
-#define F15_MSG_BASED_C1E_SUPPORT
#if OPTION_MSG_BASED_C1E == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_FAMILY10H_HY == TRUE
- #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
- #undef OPTION_MSG_BASED_C1E_FEAT
- #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
- #endif
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
- #undef OPTION_MSG_BASED_C1E_FEAT
- #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_FAMILY10H_HY == TRUE
- #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
- extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e;
- #undef F10_MSG_BASED_C1E_SUPPORT
- #define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e},
- #endif
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
- extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15MsgBasedC1e;
- #undef F15_MSG_BASED_C1E_SUPPORT
- #define F15_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15, &F15MsgBasedC1e},
- #endif
- #endif
- #endif
-
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
{
- F10_MSG_BASED_C1E_SUPPORT
- F15_MSG_BASED_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionPreserveMailboxInstall.h
index 368df9d..f797954 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionPreserveMailboxInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionPreserveMailboxInstall.h
@@ -54,47 +54,11 @@
* Check to validate the definition
*/
#define OPTION_PRESERVE_MAILBOX_FEAT
-#define F10_PRESERVE_MAILBOX_SUPPORT
-#define F15_PRESERVE_MAILBOX_SUPPORT
#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
- #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE))
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox;
- #undef OPTION_PRESERVE_MAILBOX_FEAT
- #define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox,
- #endif
- #if OPTION_FAMILY10H == TRUE
- CONST PCI_ADDR ROMDATA F10PreserveMailboxRegisters [] = {
- MAKE_SBDFO (0, 0, 0, 3, 0x168),
- MAKE_SBDFO (0, 0, 0, 3, 0x170),
- ILLEGAL_SBDFO
- };
- CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = {
- 0,
- TRUE,
- (PCI_ADDR *)&F10PreserveMailboxRegisters
- };
- #undef F10_PRESERVE_MAILBOX_SUPPORT
- #define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices},
- #endif
- #if OPTION_FAMILY15H == TRUE
- CONST PCI_ADDR ROMDATA F15PreserveMailboxRegisters [] = {
- MAKE_SBDFO (0, 0, 0, 3, 0x168),
- MAKE_SBDFO (0, 0, 0, 3, 0x170),
- ILLEGAL_SBDFO
- };
- CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = {
- 0,
- TRUE,
- (PCI_ADDR *)&F15PreserveMailboxRegisters
- };
- #undef F15_PRESERVE_MAILBOX_SUPPORT
- #define F15_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_15, &F15PreserveMailboxServices},
- #endif
+
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] =
{
- F10_PRESERVE_MAILBOX_SUPPORT
- F15_PRESERVE_MAILBOX_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable =
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionPstateInstall.h
index 116320a..19c8e9a 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionPstateInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionPstateInstall.h
@@ -54,30 +54,12 @@
* Check to validate the definition
*/
-#define F10_PSTATE_SERVICE_SUPPORT
-#define F12_PSTATE_SERVICE_SUPPORT
#define F14_PSTATE_SERVICE_SUPPORT
-#define F15_PSTATE_SERVICE_SUPPORT
#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
//
//Define Pstate CPU Family service
//
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices;
- #undef F10_PSTATE_SERVICE_SUPPORT
- #define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices},
- #endif
- #endif
-
- #ifdef OPTION_FAMILY12H
- #if OPTION_FAMILY12H == TRUE
- extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices;
- #undef F12_PSTATE_SERVICE_SUPPORT
- #define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices},
- #endif
- #endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
@@ -87,13 +69,6 @@
#endif
#endif
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15PstateServices;
- #undef F15_PSTATE_SERVICE_SUPPORT
- #define F15_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15, &F15PstateServices},
- #endif
- #endif
//
//Define ACPI Pstate objects.
//
@@ -229,10 +204,7 @@
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
{
- F10_PSTATE_SERVICE_SUPPORT
- F12_PSTATE_SERVICE_SUPPORT
F14_PSTATE_SERVICE_SUPPORT
- F15_PSTATE_SERVICE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionSwC1eInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionSwC1eInstall.h
index 34886ee..4e4b55f 100644
--- a/src/vendorcode/amd/agesa/f14/Config/OptionSwC1eInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/OptionSwC1eInstall.h
@@ -51,23 +51,9 @@
* Check to validate the definition
*/
#define OPTION_SW_C1E_FEAT
-#define F10_SW_C1E_SUPPORT
#if AGESA_ENTRY_INIT_EARLY == TRUE
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e;
- #undef OPTION_SW_C1E_FEAT
- #define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e,
- extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e;
- #undef F10_SW_C1E_SUPPORT
- #define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e},
- #endif
- #endif
- #endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] =
{
- F10_SW_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable =
diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
index 1a32ef3..947eba9 100644
--- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
@@ -72,81 +72,12 @@
*/
/* Default sockets to off */
-#define OPTION_G34_SOCKET_SUPPORT FALSE
-#define OPTION_C32_SOCKET_SUPPORT FALSE
-#define OPTION_S1G3_SOCKET_SUPPORT FALSE
-#define OPTION_S1G4_SOCKET_SUPPORT FALSE
-#define OPTION_ASB2_SOCKET_SUPPORT FALSE
-#define OPTION_FS1_SOCKET_SUPPORT FALSE
-#define OPTION_FM1_SOCKET_SUPPORT FALSE
-#define OPTION_FP1_SOCKET_SUPPORT FALSE
#define OPTION_FT1_SOCKET_SUPPORT FALSE
-#define OPTION_AM3_SOCKET_SUPPORT FALSE
/* Default families to off */
-#define OPTION_FAMILY10H FALSE
-#define OPTION_FAMILY12H FALSE
#define OPTION_FAMILY14H FALSE
-#define OPTION_FAMILY15H FALSE
-
/* Enable the appropriate socket support */
-#ifdef INSTALL_G34_SOCKET_SUPPORT
- #if INSTALL_G34_SOCKET_SUPPORT == TRUE
- #undef OPTION_G34_SOCKET_SUPPORT
- #define OPTION_G34_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_C32_SOCKET_SUPPORT
- #if INSTALL_C32_SOCKET_SUPPORT == TRUE
- #undef OPTION_C32_SOCKET_SUPPORT
- #define OPTION_C32_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_S1G3_SOCKET_SUPPORT
- #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE
- #undef OPTION_S1G3_SOCKET_SUPPORT
- #define OPTION_S1G3_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_S1G4_SOCKET_SUPPORT
- #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE
- #undef OPTION_S1G4_SOCKET_SUPPORT
- #define OPTION_S1G4_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_ASB2_SOCKET_SUPPORT
- #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE
- #undef OPTION_ASB2_SOCKET_SUPPORT
- #define OPTION_ASB2_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_FS1_SOCKET_SUPPORT
- #if INSTALL_FS1_SOCKET_SUPPORT == TRUE
- #undef OPTION_FS1_SOCKET_SUPPORT
- #define OPTION_FS1_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_FM1_SOCKET_SUPPORT
- #if INSTALL_FM1_SOCKET_SUPPORT == TRUE
- #undef OPTION_FM1_SOCKET_SUPPORT
- #define OPTION_FM1_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_FP1_SOCKET_SUPPORT
- #if INSTALL_FP1_SOCKET_SUPPORT == TRUE
- #undef OPTION_FP1_SOCKET_SUPPORT
- #define OPTION_FP1_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
#ifdef INSTALL_FT1_SOCKET_SUPPORT
#if INSTALL_FT1_SOCKET_SUPPORT == TRUE
#undef OPTION_FT1_SOCKET_SUPPORT
@@ -154,31 +85,6 @@
#endif
#endif
-#ifdef INSTALL_AM3_SOCKET_SUPPORT
- #if INSTALL_AM3_SOCKET_SUPPORT == TRUE
- #undef OPTION_AM3_SOCKET_SUPPORT
- #define OPTION_AM3_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-
-/* Enable the appropriate family support */
-// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3
-#ifdef INSTALL_FAMILY_10_SUPPORT
- #if INSTALL_FAMILY_10_SUPPORT == TRUE
- #undef OPTION_FAMILY10H
- #define OPTION_FAMILY10H TRUE
- #endif
-#endif
-
-// F12 is supported in FP1, FS1, & FM1
-#ifdef INSTALL_FAMILY_12_SUPPORT
- #if INSTALL_FAMILY_12_SUPPORT == TRUE
- #undef OPTION_FAMILY12H
- #define OPTION_FAMILY12H TRUE
- #endif
-#endif
-
// F14 is supported in FT1
#ifdef INSTALL_FAMILY_14_SUPPORT
#if INSTALL_FAMILY_14_SUPPORT == TRUE
@@ -187,30 +93,6 @@
#endif
#endif
-// F15 is supported in G34, C32, & AM3
-#ifdef INSTALL_FAMILY_15_SUPPORT
- #if INSTALL_FAMILY_15_SUPPORT == TRUE
- #undef OPTION_FAMILY15H
- #define OPTION_FAMILY15H TRUE
- #endif
-#endif
-
-
-/* Turn off families not required by socket designations */
-#if (OPTION_FAMILY10H == TRUE)
- #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
- #undef OPTION_FAMILY10H
- #define OPTION_FAMILY10H FALSE
- #endif
-#endif
-
-#if (OPTION_FAMILY12H == TRUE)
- #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE)
- #undef OPTION_FAMILY12H
- #define OPTION_FAMILY12H FALSE
- #endif
-#endif
-
#if (OPTION_FAMILY14H == TRUE)
#if (OPTION_FT1_SOCKET_SUPPORT == FALSE)
#undef OPTION_FAMILY14H
@@ -218,62 +100,8 @@
#endif
#endif
-#if (OPTION_FAMILY15H == TRUE)
- #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
- #undef OPTION_FAMILY15H
- #define OPTION_FAMILY15H FALSE
- #endif
-#endif
-
/* Check for invalid combinations of socket/family */
-#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
- #error No G34 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
- #error No C32 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == FALSE)
- #error No S1G3 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == FALSE)
- #error No S1G4 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == FALSE)
- #error No ASB2 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY12H == FALSE)
- #error No FS1 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY12H == FALSE)
- #error No FM1 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY12H == FALSE)
- #error No FP1 supported families included in the build
- #endif
-#endif
#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
#if (OPTION_FAMILY14H == FALSE)
@@ -281,13 +109,6 @@
#endif
#endif
-#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
- #error No AM3 supported families included in the build
- #endif
-#endif
-
-
/* Process AGESA private data
*
* Turn on appropriate CPU models and memory controllers,
@@ -295,26 +116,10 @@
*/
/* Default all models to off */
-#define OPTION_FAMILY10H_BL FALSE
-#define OPTION_FAMILY10H_DA FALSE
-#define OPTION_FAMILY10H_HY FALSE
-#define OPTION_FAMILY10H_PH FALSE
-#define OPTION_FAMILY10H_RB FALSE
-#define OPTION_FAMILY12H_LN FALSE
#define OPTION_FAMILY14H_ON FALSE
-#define OPTION_FAMILY15H_OR FALSE
/* Default all memory controllers to off */
-#define OPTION_MEMCTLR_DR FALSE
-#define OPTION_MEMCTLR_HY FALSE
-#define OPTION_MEMCTLR_OR FALSE
-#define OPTION_MEMCTLR_C32 FALSE
-#define OPTION_MEMCTLR_DA FALSE
-#define OPTION_MEMCTLR_LN FALSE
#define OPTION_MEMCTLR_ON FALSE
-#define OPTION_MEMCTLR_Ni FALSE
-#define OPTION_MEMCTLR_PH FALSE
-#define OPTION_MEMCTLR_RB FALSE
/* Default all memory controls to off */
#define OPTION_HW_WRITE_LEV_TRAINING FALSE
@@ -364,551 +169,6 @@
#define OPTION_GFX_RECOVERY FALSE
/* Enable all private controls based on socket/family enables */
-#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == TRUE)
- #undef OPTION_FAMILY10H_HY
- #define OPTION_FAMILY10H_HY TRUE
- #undef OPTION_MEMCTLR_HY
- #define OPTION_MEMCTLR_HY TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_MULTISOCKET
- #define OPTION_MULTISOCKET TRUE
- #undef OPTION_SRAT
- #define OPTION_SRAT TRUE
- #undef OPTION_SLIT
- #define OPTION_SLIT TRUE
- #undef OPTION_HT_ASSIST
- #define OPTION_HT_ASSIST TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_MSG_BASED_C1E
- #define OPTION_MSG_BASED_C1E TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_RDIMMS
- #define OPTION_RDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_PARALLEL_TRAINING
- #define OPTION_PARALLEL_TRAINING TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
- #if (OPTION_FAMILY15H == TRUE)
- #undef OPTION_FAMILY15H_OR
- #define OPTION_FAMILY15H_OR TRUE
- #undef OPTION_MEMCTLR_OR
- #define OPTION_MEMCTLR_OR TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_CONTINOUS_PATTERN_GENERATION
- #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
- #undef OPTION_HW_DQS_REC_EN_TRAINING
- #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_MULTISOCKET
- #define OPTION_MULTISOCKET TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
- #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
- #undef OPTION_SRAT
- #define OPTION_SRAT TRUE
- #undef OPTION_SLIT
- #define OPTION_SLIT TRUE
- #undef OPTION_HT_ASSIST
- #define OPTION_HT_ASSIST TRUE
- #undef OPTION_ATM_MODE
- #define OPTION_ATM_MODE TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_MSG_BASED_C1E
- #define OPTION_MSG_BASED_C1E TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_RDIMMS
- #define OPTION_RDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_LRDIMMS
- #define OPTION_LRDIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == TRUE)
- #undef OPTION_FAMILY10H_HY
- #define OPTION_FAMILY10H_HY TRUE
- #undef OPTION_MEMCTLR_C32
- #define OPTION_MEMCTLR_C32 TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_ADDR_TO_CS_TRANSLATOR
- #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
- #undef OPTION_MULTISOCKET
- #define OPTION_MULTISOCKET TRUE
- #undef OPTION_SRAT
- #define OPTION_SRAT TRUE
- #undef OPTION_SLIT
- #define OPTION_SLIT TRUE
- #undef OPTION_HT_ASSIST
- #define OPTION_HT_ASSIST TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_MSG_BASED_C1E
- #define OPTION_MSG_BASED_C1E TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_RDIMMS
- #define OPTION_RDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_PARALLEL_TRAINING
- #define OPTION_PARALLEL_TRAINING TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
- #if (OPTION_FAMILY15H == TRUE)
- #undef OPTION_FAMILY15H_OR
- #define OPTION_FAMILY15H_OR TRUE
- #undef OPTION_MEMCTLR_OR
- #define OPTION_MEMCTLR_OR TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_CONTINOUS_PATTERN_GENERATION
- #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
- #undef OPTION_HW_DQS_REC_EN_TRAINING
- #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_ADDR_TO_CS_TRANSLATOR
- #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
- #undef OPTION_MULTISOCKET
- #define OPTION_MULTISOCKET TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
- #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
- #undef OPTION_SRAT
- #define OPTION_SRAT TRUE
- #undef OPTION_SLIT
- #define OPTION_SLIT TRUE
- #undef OPTION_HT_ASSIST
- #define OPTION_HT_ASSIST TRUE
- #undef OPTION_ATM_MODE
- #define OPTION_ATM_MODE TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_MSG_BASED_C1E
- #define OPTION_MSG_BASED_C1E TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_RDIMMS
- #define OPTION_RDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_LRDIMMS
- #define OPTION_LRDIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == TRUE)
- #undef OPTION_FAMILY10H_BL
- #define OPTION_FAMILY10H_BL TRUE
- #undef OPTION_FAMILY10H_DA
- #define OPTION_FAMILY10H_DA TRUE
- #undef OPTION_MEMCTLR_DA
- #define OPTION_MEMCTLR_DA TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_PARALLEL_TRAINING
- #define OPTION_PARALLEL_TRAINING TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == TRUE)
- #undef OPTION_FAMILY10H_BL
- #define OPTION_FAMILY10H_BL TRUE
- #undef OPTION_FAMILY10H_DA
- #define OPTION_FAMILY10H_DA TRUE
- #undef OPTION_MEMCTLR_DA
- #define OPTION_MEMCTLR_DA TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == TRUE)
- #undef OPTION_FAMILY10H_BL
- #define OPTION_FAMILY10H_BL TRUE
- #undef OPTION_FAMILY10H_DA
- #define OPTION_FAMILY10H_DA TRUE
- #undef OPTION_MEMCTLR_Ni
- #define OPTION_MEMCTLR_Ni TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY12H == TRUE)
- #undef OPTION_FAMILY12H_LN
- #define OPTION_FAMILY12H_LN TRUE
- #undef OPTION_MEMCTLR_LN
- #define OPTION_MEMCTLR_LN TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_CONTINOUS_PATTERN_GENERATION
- #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
- #undef OPTION_HW_DQS_REC_EN_TRAINING
- #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_GFX_RECOVERY
- #define OPTION_GFX_RECOVERY TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_S3SCRIPT
- #define OPTION_S3SCRIPT TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY12H == TRUE)
- #undef OPTION_FAMILY12H_LN
- #define OPTION_FAMILY12H_LN TRUE
- #undef OPTION_MEMCTLR_LN
- #define OPTION_MEMCTLR_LN TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_CONTINOUS_PATTERN_GENERATION
- #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
- #undef OPTION_HW_DQS_REC_EN_TRAINING
- #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_GFX_RECOVERY
- #define OPTION_GFX_RECOVERY TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_S3SCRIPT
- #define OPTION_S3SCRIPT TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY12H == TRUE)
- #undef OPTION_FAMILY12H_LN
- #define OPTION_FAMILY12H_LN TRUE
- #undef OPTION_MEMCTLR_LN
- #define OPTION_MEMCTLR_LN TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_CONTINOUS_PATTERN_GENERATION
- #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
- #undef OPTION_HW_DQS_REC_EN_TRAINING
- #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_ADDR_TO_CS_TRANSLATOR
- #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
- #undef OPTION_GFX_RECOVERY
- #define OPTION_GFX_RECOVERY TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_S3SCRIPT
- #define OPTION_S3SCRIPT TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
#if (OPTION_FAMILY14H == TRUE)
@@ -955,128 +215,7 @@
#endif
#endif
-#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == TRUE)
- #undef OPTION_FAMILY10H_BL
- #define OPTION_FAMILY10H_BL TRUE
- #undef OPTION_FAMILY10H_DA
- #define OPTION_FAMILY10H_DA TRUE
- #undef OPTION_FAMILY10H_PH
- #define OPTION_FAMILY10H_PH TRUE
- #undef OPTION_FAMILY10H_RB
- #define OPTION_FAMILY10H_RB TRUE
- #undef OPTION_MEMCTLR_RB
- #define OPTION_MEMCTLR_RB TRUE
- #undef OPTION_MEMCTLR_DA
- #define OPTION_MEMCTLR_DA TRUE
- #undef OPTION_MEMCTLR_PH
- #define OPTION_MEMCTLR_PH TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_PARALLEL_TRAINING
- #define OPTION_PARALLEL_TRAINING TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
- #if (OPTION_FAMILY15H == TRUE)
- #undef OPTION_FAMILY15H_OR
- #define OPTION_FAMILY15H_OR TRUE
- #undef OPTION_MEMCTLR_OR
- #define OPTION_MEMCTLR_OR TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_CONTINOUS_PATTERN_GENERATION
- #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
- #undef OPTION_HW_DQS_REC_EN_TRAINING
- #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
- #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_ADDR_TO_CS_TRANSLATOR
- #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_MSG_BASED_C1E
- #define OPTION_MSG_BASED_C1E TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_RDIMMS
- #define OPTION_RDIMMS TRUE
- #undef OPTION_LRDIMMS
- #define OPTION_LRDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
+#if (OPTION_FAMILY14H == TRUE)
#undef GNB_SUPPORT
#define GNB_SUPPORT TRUE
#endif