mb/acer/g43t-am3: add Acer G43T-AM3 mainboard
Adds a new port for the Aspire G43T-AM3. It is from an Aspire M3800
desktop model of which I only own the mainboard. The silkscreen label
calls it "G45T/G43T-AM3 V:1.0". In DMI data it is additionally called
Acer EG43M.
The Aspire M5800 model seems to use the same mainboard. The BIOS you can
download from Acer is identical for both.
Various similar mainboards by Acer exist: G41T-AM, G43T-AM, G43T-AM4,
Q45T-AM, to name a few. ECS has some models that are obiously based on
the same design, e.g. G43T-WM and G43T-M.
This model is a microATX-sized board with an LGA 775 socket, four DDR3
DIMM slots, one PCIe x16 slot, one PCIe x1 slot and two PCI slots based
on the Intel G43 chipset.
The port was started by copying mb/intel/dg43gt (not going to lie here)
and adapting things by looking at dumps from the system when running
with the vendor BIOS. Serial console output is possible by soldering to
a point at the corresponding Super I/O pin.
The service manual for the board was helpful for setting the correct PCI
IRQ links. It can be found publicly on the internet as the "Acer Aspire
M3800 Service Manual".
Working:
- CPUs from Pentium Dual-Core E2160 to Core 2 Quad Q9550 at FSB1333
- Native raminit
- All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB)
- PS/2 mouse
- PS/2 keyboard (needs CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500)
- USB ports (8 internal, 4 external)
- All six SATA ports
- Intel GbE
- Both PCI ports with various cards (Ethernet, audio, USB, VGA)
- Integrated graphics (libgfxinit)
- HDMI and VGA ports
- boot with PCIe graphics and SeaBIOS
- boot with PCI VGA and SeaBIOS
- Both PCIe ports
- Flashing with flashrom
- Rear audio output
- SeaBIOS 1.14.0 to boot slackware64
- SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS)
- Temperature readings (including PECI)
- Super I/O EC automatic fan control
- S3 suspend/resume
- Poweroff
Not working:
- Resource issues with the VGA BIOS of a PCI rv100-based card
- Super I/O voltage reading conversions
Untested:
- The other audio jacks or the front panel header
- On-board Firewire
- EHCI debug
- VBT (was extracted and added, but don't know how to test)
- Super I/O GPIOs
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I846cf5f4f1ef27fc644676a4c6f7a333e061f6cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb
new file mode 100644
index 0000000..4266861
--- /dev/null
+++ b/src/mainboard/acer/g43t-am3/devicetree.cb
@@ -0,0 +1,161 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/x4x # Northbridge
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x # CPU
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0 on # PCI domain
+ subsystemid 0x8086 0x0028 inherit
+ device pci 0.0 on end # Host Bridge
+ device pci 2.0 on end # Integrated graphics controller
+ device pci 2.1 on end # Integrated graphics controller 2
+ device pci 3.0 off end # ME
+ device pci 3.1 off end # ME
+ chip southbridge/intel/i82801jx # Southbridge
+ register "gpe0_en" = "0x40"
+
+ # Set AHCI mode.
+ register "sata_port_map" = "0x3f"
+ register "sata_clock_request" = "0"
+
+ # Enable PCIe ports 0,1 as slots.
+ register "pcie_slot_implemented" = "0x3"
+
+ # "Additional LPC IO decode ranges": used for SuperIO's
+ # Environment Controller on 0xa15/0xa16
+ register "gen1_dec" = "0x00fc0a01"
+
+ device pci 19.0 on end # GBE
+ device pci 1a.0 on end # USB
+ device pci 1a.1 on end # USB
+ device pci 1a.2 on end # USB
+ device pci 1a.7 on end # USB
+ device pci 1b.0 on end # Audio
+ device pci 1c.0 on end # PCIe 1
+ device pci 1c.1 on end # PCIe 2
+ device pci 1c.2 off end # PCIe 3
+ device pci 1c.3 off end # PCIe 4
+ device pci 1c.4 off end # PCIe 5
+ device pci 1c.5 off end # PCIe 6
+ device pci 1d.0 on end # USB
+ device pci 1d.1 on end # USB
+ device pci 1d.2 on end # USB
+ device pci 1d.7 on end # USB
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip superio/ite/it8720f # Super I/O
+ register "ec.smbus_en" = "1"
+ register "ec.smbus_24mhz" = "1"
+ register "TMPIN1.mode" = "THERMAL_DIODE"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN3.mode" = "THERMAL_PECI"
+ register "TMPIN3.offset" = "100"
+ register "TMPIN3.min" = "0"
+ register "TMPIN3.max" = "100"
+
+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC" # CPU fan
+ register "FAN1.smart.tmpin" = "3"
+ register "FAN1.smart.tmp_off" = "0"
+ register "FAN1.smart.tmp_start" = "50"
+ register "FAN1.smart.tmp_full" = "90"
+ register "FAN1.smart.tmp_delta" = "3"
+ register "FAN1.smart.full_lmt" = "1"
+ register "FAN1.smart.smoothing" = "0"
+ register "FAN1.smart.pwm_start" = "30"
+ register "FAN1.smart.slope" = "0x0d"
+ register "FAN2.mode" = "FAN_SMART_AUTOMATIC" # System fan
+ register "FAN2.smart.tmpin" = "2"
+ register "FAN2.smart.tmp_off" = "0"
+ register "FAN2.smart.tmp_start" = "40"
+ register "FAN2.smart.tmp_full" = "90"
+ register "FAN2.smart.tmp_delta" = "2"
+ register "FAN2.smart.full_lmt" = "0"
+ register "FAN2.smart.smoothing" = "0"
+ register "FAN2.smart.pwm_start" = "48"
+ register "FAN2.smart.slope" = "0x20"
+ register "FAN3.mode" = "FAN_MODE_OFF" # Not connected
+
+ register "ec.vin_mask" = "VIN_ALL"
+
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 off end # COM 1
+ device pnp 2e.2 off end # COM 2
+ device pnp 2e.3 off end # Parallel port
+ device pnp 2e.4 on # Environment controller
+ io 0x60 = 0xa10
+ io 0x62 = 0xa00
+ irq 0x70 = 0x00
+ irq 0xf0 = 0x00
+ irq 0xf1 = 0x00
+ irq 0xf2 = 0x00
+ irq 0xf3 = 0x00
+ irq 0xf4 = 0x60
+ irq 0xf5 = 0x00
+ irq 0xf6 = 0x00
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x060
+ irq 0x70 = 0x1
+ io 0x62 = 0x064
+ irq 0xf0 = 0x00
+ end
+ device pnp 2e.6 on # Mouse
+ irq 0x70 = 0x0c
+ irq 0xf0 = 0x00
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x000
+ io 0x62 = 0xa20
+ io 0x64 = 0xa30
+ irq 0xc0 = 0x01 # Simple IO Set 1
+ irq 0xc1 = 0x0c # Simple IO Set 2
+ irq 0xc2 = 0x70 # Simple IO Set 3
+ irq 0xc3 = 0x00 # Simple IO Set 4
+ irq 0xc8 = 0x01 # Simple IO Set 1 Output
+ irq 0xc9 = 0x0c # Simple IO Set 2 Output
+ irq 0xca = 0x00 # Simple IO Set 3 Output
+ irq 0xcb = 0x00 # Simple IO Set 4 Output
+ irq 0xf0 = 0x00
+ irq 0xf1 = 0x00
+ irq 0xf2 = 0x00
+ irq 0xf3 = 0x00
+ irq 0xf4 = 0x00
+ irq 0xf5 = 0x00
+ irq 0xf6 = 0x00
+ irq 0xf7 = 0x00
+ irq 0xf8 = 0x12
+ irq 0xf9 = 0x02
+ irq 0xfa = 0x13
+ irq 0xfb = 0x02
+ #irq 0xfc = 0xef # VID Input
+ irq 0xfd = 0x00
+ irq 0xfe = 0x00
+ end
+ device pnp 2e.a off end # CIR
+ end
+ end
+ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5)
+ device pci 1f.3 on # SMBus
+ chip drivers/i2c/ck505 # IDT CV194
+ register "mask" = "{ 0xff, 0xff, 0xff, 0x00,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x00, 0xff, 0xff, 0xff,
+ 0x00, 0xff }"
+ register "regs" = "{ 0x57, 0xd9, 0xfe, 0xff,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x00, 0x24, 0x7d, 0x96,
+ 0x00, 0x9d }"
+ device i2c 69 on end
+ end
+ end
+ device pci 1f.4 off end
+ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode)
+ device pci 1f.6 off end # Thermal Subsystem
+ end
+ end
+end