tree ce9e9e0345391148d4918238b7325051ba0dcd8d
parent 5926fb5035aca828711f6b3edb1c4242bb547f7e
author Nick Vaccaro <nvaccaro@google.com> 1586209327 -0700
committer Patrick Georgi <pgeorgi@google.com> 1586857841 +0000

mb/google/volteer: fix incorrect fields in SPDs

According to Intel Document #616599,
  1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10
     columns)
  2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel
     x16)

This change fixes those two values in the existing SPD files for
Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a
generic SPD).

BUG=b:152827558
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
Volteer to kernel.

Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>