commit ba3b2f8fd86b54486f3821682f359281382d75ac
author Shaik Shahina <shahina.shaik@intel.com> Wed Dec 07 15:04:01 2022 +0530
committer Felix Held <felix-coreboot@felixheld.de> Fri Dec 09 20:45:46 2022 +0000
tree bc272d69b879b2271eeb7fc61c1a6216a21c4968
parent c8acbdc60c040a794fc160afb3a0256717f04858

vc/intel/fsp: Update ADL N FSP headers from v3343.04 to v3343.05

Update generated FSP headers for Alder Lake N from v3343.04 to v3343.05.

Changes include:
-FspsUpd.h : Update UfsEnable UPD description in comments

BUG=b:228110908
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa.

Change-Id: Ieff33df2d2b0884a9788e05e06da5bdae1be08de
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70446
Reviewed-by: Shahina Shaik <shahina.shaik@intel.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h

diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
index 057fce7..02b544a 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
@@ -2224,7 +2224,8 @@
   UINT8                       SataRstPcieDeviceResetDelay[3];
 
 /** Offset 0x0A42 - UFS enable/disable
-  PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
+  Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller
+  0 and (0,1) to enable controller 1
   $EN_DIS
 **/
   UINT8                       UfsEnable[2];