src/southbridge: Code formating
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index d5dcde0..c122d2a 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -117,7 +117,7 @@
int timeout = 1000;
- while(timeout--) {
+ while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@@ -145,7 +145,7 @@
/* Use a 1msec timeout */
int timeout = 1000;
- while(timeout--) {
+ while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 1106912..9041816 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -125,7 +125,7 @@
pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 83c99e0..23915c3 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -445,7 +445,7 @@
print_cap("IntelR Power Sharing Technology (MPC)",
cap.caps_sku.intel_mpc);
print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+ print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
print_cap("IPV6", cap.caps_sku.ipv6);
print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 4dbe8ed..220a176 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -703,7 +703,7 @@
if (intel_mei_setup(dev) < 0)
break;
- if(intel_me_read_mbp(&mbp_data))
+ if (intel_me_read_mbp(&mbp_data))
break;
#if CONFIG_CHROMEOS && 0 /* DISABLED */
@@ -893,7 +893,7 @@
default:
printk(BIOS_ERR, "ME: unknown mbp item id 0x%x! Skipping\n",
mbp_item_id);
- while(copy_size--)
+ while (copy_size--)
read_cb();
continue;
}
@@ -904,7 +904,7 @@
buffer_room, copy_size, mbp_item_id);
return -1;
}
- while(copy_size--)
+ while (copy_size--)
*copy_addr++ = read_cb();
}
@@ -914,7 +914,7 @@
{
int cntr = 0;
- while(host.interrupt_generate) {
+ while (host.interrupt_generate) {
read_host_csr(&host);
cntr++;
}
diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c
index daabbbc..804fb81 100644
--- a/src/southbridge/intel/bd82x6x/reset.c
+++ b/src/southbridge/intel/bd82x6x/reset.c
@@ -19,10 +19,10 @@
void soft_reset(void)
{
- outb(0x04, 0xcf9);
+ outb(0x04, 0xcf9);
}
void hard_reset(void)
{
- outb(0x06, 0xcf9);
+ outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index bc19b78..0478285 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -271,37 +271,37 @@
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
- val = pci_read_config32(dev, PCI_VENDOR_ID);
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
static void southbridge_gate_memory_reset_real(int offset,
@@ -863,7 +863,7 @@
}
}
- if(dump) {
+ if (dump) {
dump_smi_status(smi_sts);
}