commit | ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 | [log] [tgz] |
---|---|---|
author | Elyes HAOUAS <ehaouas@noos.fr> | Wed Aug 31 19:22:16 2016 +0200 |
committer | Martin Roth <martinroth@google.com> | Wed Aug 31 20:22:46 2016 +0200 |
tree | 9f7e4416b63e26ee3f4df6f9a61ab55f377bcb5f | |
parent | 2e4d80687dd79890c7c9edad8dbaf6e89edf2afc [diff] [blame] |
src/southbridge: Code formating Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index 9756483..b6b2bd3 100644 --- a/src/southbridge/amd/common/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c
@@ -58,7 +58,7 @@ { u8 byte; - if(picr_data_ptr == NULL || intr_data_ptr == NULL){ + if (picr_data_ptr == NULL || intr_data_ptr == NULL){ printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n" "'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n"); return;