| commit | ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 | [log] [tgz] |
|---|---|---|
| author | Elyes HAOUAS <ehaouas@noos.fr> | Wed Aug 31 19:22:16 2016 +0200 |
| committer | Martin Roth <martinroth@google.com> | Wed Aug 31 20:22:46 2016 +0200 |
| tree | 9f7e4416b63e26ee3f4df6f9a61ab55f377bcb5f | |
| parent | 2e4d80687dd79890c7c9edad8dbaf6e89edf2afc [diff] [blame] |
src/southbridge: Code formating Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index 9a98760..a5c42b7 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c
@@ -32,7 +32,7 @@ int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect;