diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index 0e351a9..5dca211 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -67,8 +67,6 @@
 	if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
 		lpc_disable_spi_rom_sharing();
 
-	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
-		espi_clear_decodes();
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
 		espi_setup();
-	}
 }
diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h
index f5e7d31..435b81f 100644
--- a/src/soc/amd/common/block/include/amdblocks/espi.h
+++ b/src/soc/amd/common/block/include/amdblocks/espi.h
@@ -101,13 +101,6 @@
 int espi_open_mmio_window(uint32_t base, size_t size);
 
 /*
- * Clear all configured eSPI memory and I/O decode ranges.  This is useful for changing
- * the decodes, or if something else has previously setup decode windows that conflict
- * with the windows that coreboot needs.
- */
-void espi_clear_decodes(void);
-
-/*
  * In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading
  * SPIBASE. This is required for cases where verstage runs on PSP.
  */
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 0b690b8..f120082 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -98,7 +98,7 @@
 	return -1;
 }
 
-void espi_clear_decodes(void)
+static void espi_clear_decodes(void)
 {
 	unsigned int idx;
 
@@ -894,6 +894,7 @@
 	espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI);
 	espi_write32(ESPI_SLAVE0_INT_EN, 0);
 	espi_clear_status();
+	espi_clear_decodes();
 
 	/*
 	 * Boot sequence: Step 1