soc/intel/xeon_sp: Add P2SB definition for SPR-SP
Change-Id: I2ece7aac4339266068d4fc8fb1c58d0573eb2895
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
diff --git a/src/soc/intel/xeon_sp/include/soc/p2sb.h b/src/soc/intel/xeon_sp/include/soc/p2sb.h
index 3bdd453..1be1b9b 100644
--- a/src/soc/intel/xeon_sp/include/soc/p2sb.h
+++ b/src/soc/intel/xeon_sp/include/soc/p2sb.h
@@ -3,14 +3,18 @@
#include <commonlib/helpers.h>
/*
- * Currently all known xeon-sp CPUs use C620 PCH. These definitions
- * come from C620 datasheet (Intel Doc #336067-007US)
+ * CPX-SP and SKX-SP use LBG PCH, while SPR-SP uses EBG PCH.
+ * These definitions come from LBG datasheet (Intel Doc #336067-007US)
+ * and Emmitsburg datasheet (Intel Doc #606161).
*/
#define HPTC_OFFSET 0x60
#define HPTC_ADDR_ENABLE_BIT (1 << 7)
-#define PCH_P2SB_EPMASK0 0xb0
#define P2SB_SIZE (16 * MiB)
-
#define P2SBC 0xe0
#define SBILOCK (1 << 31)
+#if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP)
+#define PCH_P2SB_EPMASK0 0x220
+#else
+#define PCH_P2SB_EPMASK0 0xb0
+#endif