nb/intel/sandybridge,haswell: Use chromeos_reserve_ram_oops()
Communicate the RAMOOPS section via ChromeOS GNVS.
Change-Id: I75170e6e34c20db88efa268080d2c38916b31f37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index bc1a1c8..d0faa79 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -182,11 +182,6 @@
Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
-
-#if CONFIG(CHROMEOS_RAMOOPS)
- Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
- CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
-#endif
})
// Current Resource Settings
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 61ad236..c00c801 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -14,6 +14,7 @@
#include <boot/tables.h>
#include <security/intel/txt/txt_register.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "chip.h"
#include "haswell.h"
@@ -335,11 +336,9 @@
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
-#if CONFIG(CHROMEOS_RAMOOPS)
- reserved_ram_resource(dev, index++,
- CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
- CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
-#endif
+ if (CONFIG(CHROMEOS_RAMOOPS))
+ chromeos_reserve_ram_oops(dev, index++);
+
*resource_cnt = index;
}
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
index 5d7a777..cf1d61c 100644
--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -20,11 +20,6 @@
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
-#if CONFIG(CHROMEOS_RAMOOPS)
- Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
- CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
-#endif
-
/* Required for SandyBridge sighting 3715511 */
Memory32Fixed(ReadWrite, 0x20000000, 0x00200000)
Memory32Fixed(ReadWrite, 0x40000000, 0x00200000)
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 2274355..ead3c67 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -14,6 +14,7 @@
#include "chip.h"
#include "sandybridge.h"
#include <cpu/intel/smm_reloc.h>
+#include <vendorcode/google/chromeos/chromeos.h>
/* IGD UMA memory */
static uint64_t uma_memory_base = 0;
@@ -67,11 +68,8 @@
reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
-#if CONFIG(CHROMEOS_RAMOOPS)
- reserved_ram_resource(dev, index++,
- CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
- CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
-#endif
+ if (CONFIG(CHROMEOS_RAMOOPS))
+ chromeos_reserve_ram_oops(dev, index++);
if (is_sandybridge()) {
/* Required for SandyBridge sighting 3715511 */