diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index 328464a..baa4ae3 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -1,17 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <arch/bootblock.h>
+#include <arch/mmio.h>
 #include <device/pci_ops.h>
+
 #include "x4x.h"
 #include "iomap.h"
 
 void bootblock_early_northbridge_init(void)
 {
-	uint32_t reg32;
-
 	/* Disable LaGrande Technology (LT) */
-	reg32 = TPM32(0);
+	read32((void *)TPM_BASE_ADDRESS);
 
-	reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1;
+	const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1;
 	pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);
 }
diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/iomap.h
index d016cf7..22a675f 100644
--- a/src/northbridge/intel/x4x/iomap.h
+++ b/src/northbridge/intel/x4x/iomap.h
@@ -8,7 +8,6 @@
 #define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
 #define DEFAULT_HECIBAR		0xfed10000
 
-#define TPMBASE 0xfed40000
-#define TPM32(x) (*((volatile u32 *)(TPMBASE + (x))))
+#define TPM_BASE_ADDRESS	0xfed40000
 
 #endif /* X4X_IOMAP_H */