soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
Base code is based of Intel Alder Lake SOC code.
List of changes:
1. Add required Meteor Lake SoC programming till bootblock
2. Include only required headers into include/soc
3. Include MTL-P related DID, BDF
4. Ref: Processor EDS documents
vol1 #621483, vol2 #640858
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
new file mode 100644
index 0000000..2b3a5b3
--- /dev/null
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -0,0 +1,132 @@
+config SOC_INTEL_METEORLAKE
+ bool
+
+if SOC_INTEL_METEORLAKE
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_X86
+ select BOOT_DEVICE_SUPPORTS_WRITES
+ select INTEL_DESCRIPTOR_MODE_CAPABLE
+ select IDT_IN_EVERY_STAGE
+ select INTEL_CAR_NEM
+ select MICROCODE_BLOB_UNDISCLOSED
+ select SOC_INTEL_COMMON
+ select SOC_INTEL_COMMON_BLOCK_CAR
+ select SOC_INTEL_COMMON_BLOCK_CPU
+ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
+ select SOC_INTEL_COMMON_BLOCK_SA
+ select SOC_INTEL_COMMON_PCH_BASE
+ select SOC_INTEL_COMMON_RESET
+ select SSE2
+ select SUPPORT_CPU_UCODE_IN_CBFS
+ select TSC_MONOTONIC_TIMER
+ select UDELAY_TSC
+
+config DCACHE_RAM_BASE
+ default 0xfef00000
+
+config DCACHE_RAM_SIZE
+ default 0xc0000
+ help
+ The size of the cache-as-ram region required during bootblock
+ and/or romstage.
+
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x80400
+ help
+ The amount of anticipated stack usage in CAR by bootblock and
+ other stages. In the case of FSP_USES_CB_STACK default value will be
+ sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
+ (~1KiB).
+
+config FSP_TEMP_RAM_SIZE
+ hex
+ default 0x20000
+ help
+ The amount of anticipated heap usage in CAR by FSP.
+ Refer to Platform FSP integration guide document to know
+ the exact FSP requirement for Heap setup.
+
+config IFD_CHIPSET
+ string
+ default "mtl"
+
+config IED_REGION_SIZE
+ hex
+ default 0x400000
+
+config HEAP_SIZE
+ hex
+ default 0x10000
+
+config PCR_BASE_ADDRESS
+ hex
+ default 0xe0000000
+ help
+ This option allows you to select MMIO Base Address of sideband bus.
+
+config ECAM_MMCONF_BASE_ADDRESS
+ default 0xc0000000
+
+config CPU_BCLK_MHZ
+ int
+ default 100
+
+config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
+ int
+ default 120
+
+config CPU_XTAL_HZ
+ default 38400000
+
+config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
+ int
+ default 133
+
+config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
+ int
+ default 2
+
+config SOC_INTEL_I2C_DEV_MAX
+ int
+ default 6
+
+config SOC_INTEL_UART_DEV_MAX
+ int
+ default 3
+
+config SOC_INTEL_USB2_DEV_MAX
+ int
+ default 10
+
+config SOC_INTEL_USB3_DEV_MAX
+ int
+ default 2
+
+config CONSOLE_UART_BASE_ADDRESS
+ hex
+ default 0xfe03e000
+ depends on INTEL_LPSS_UART_FOR_CONSOLE
+
+# Clock divider parameters for 115200 baud rate
+# Baudrate = (UART source clcok * M) /(N *16)
+# MTL UART source clock: 120MHz
+config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
+ hex
+ default 0x25a
+
+config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
+ hex
+ default 0x7fff
+
+config CBFS_SIZE
+ hex
+ default 0x200000
+
+config PRERAM_CBMEM_CONSOLE_SIZE
+ hex
+ default 0x1400
+
+endif
diff --git a/src/soc/intel/meteorlake/Makefile.inc b/src/soc/intel/meteorlake/Makefile.inc
new file mode 100644
index 0000000..cc246eb
--- /dev/null
+++ b/src/soc/intel/meteorlake/Makefile.inc
@@ -0,0 +1,11 @@
+ifeq ($(CONFIG_SOC_INTEL_METEORLAKE),y)
+
+bootblock-y += bootblock/bootblock.c
+bootblock-y += bootblock/ioe_die.c
+bootblock-y += bootblock/report_platform.c
+bootblock-y += bootblock/soc_die.c
+
+CPPFLAGS_common += -I$(src)/soc/intel/meteorlake
+CPPFLAGS_common += -I$(src)/soc/intel/meteorlake/include
+
+endif
diff --git a/src/soc/intel/meteorlake/bootblock/bootblock.c b/src/soc/intel/meteorlake/bootblock/bootblock.c
new file mode 100644
index 0000000..74e9dca
--- /dev/null
+++ b/src/soc/intel/meteorlake/bootblock/bootblock.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/bootblock.h>
+
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+ /* Call lib/bootblock.c main */
+ bootblock_main_with_basetime(base_timestamp);
+}
+
+void bootblock_soc_early_init(void)
+{
+ bootblock_ioe_die_early_init();
+ bootblock_soc_die_early_init();
+}
+
+void bootblock_soc_init(void)
+{
+ report_platform_info();
+ bootblock_soc_die_init();
+}
diff --git a/src/soc/intel/meteorlake/bootblock/ioe_die.c b/src/soc/intel/meteorlake/bootblock/ioe_die.c
new file mode 100644
index 0000000..d1f85ff
--- /dev/null
+++ b/src/soc/intel/meteorlake/bootblock/ioe_die.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/p2sb.h>
+#include <soc/bootblock.h>
+
+void bootblock_ioe_die_early_init(void)
+{
+ ioe_p2sb_enable_bar();
+}
diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c
new file mode 100644
index 0000000..564d186
--- /dev/null
+++ b/src/soc/intel/meteorlake/bootblock/report_platform.c
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cpu.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <cpu/intel/cpu_ids.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/name.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/bootblock.h>
+#include <soc/pci_devs.h>
+
+static struct {
+ u32 cpuid;
+ const char *name;
+} cpu_table[] = {
+ { CPUID_METEORLAKE_A0_1, "MeteorLake A0" },
+ { CPUID_METEORLAKE_A0_2, "MeteorLake A0" },
+};
+
+static struct {
+ u16 mchid;
+ const char *name;
+} mch_table[] = {
+ { PCI_DID_INTEL_MTL_M_ID, "MeteorLake M" },
+ { PCI_DID_INTEL_MTL_P_ID_1, "MeteorLake P" },
+ { PCI_DID_INTEL_MTL_P_ID_2, "MeteorLake P" },
+};
+
+static struct {
+ u16 espiid;
+ const char *name;
+} pch_table[] = {
+ { PCI_DID_INTEL_MTL_ESPI_0, "MeteorLake SOC" },
+ { PCI_DID_INTEL_MTL_ESPI_1, "MeteorLake SOC" },
+ { PCI_DID_INTEL_MTL_ESPI_2, "MeteorLake SOC" },
+ { PCI_DID_INTEL_MTL_ESPI_3, "MeteorLake SOC" },
+ { PCI_DID_INTEL_MTL_ESPI_4, "MeteorLake SOC" },
+ { PCI_DID_INTEL_MTL_ESPI_5, "MeteorLake SOC" },
+ { PCI_DID_INTEL_MTL_ESPI_6, "MeteorLake SOC" },
+ { PCI_DID_INTEL_MTL_ESPI_7, "MeteorLake SOC" },
+};
+
+static struct {
+ u16 igdid;
+ const char *name;
+} igd_table[] = {
+ { PCI_DID_INTEL_MTL_M_GT2, "MeteorLake-M GT2" },
+ { PCI_DID_INTEL_MTL_P_GT2_1, "MeteorLake-P GT2" },
+ { PCI_DID_INTEL_MTL_P_GT2_2, "MeteorLake-P GT2" },
+};
+
+static inline uint8_t get_dev_revision(pci_devfn_t dev)
+{
+ return pci_read_config8(dev, PCI_REVISION_ID);
+}
+
+static inline uint16_t get_dev_id(pci_devfn_t dev)
+{
+ return pci_read_config16(dev, PCI_DEVICE_ID);
+}
+
+static void report_cpu_info(void)
+{
+ u32 i, cpu_id, cpu_feature_flag;
+ char cpu_name[49];
+ int vt, txt, aes;
+ static const char *const mode[] = {"NOT ", ""};
+ const char *cpu_type = "Unknown";
+
+ fill_processor_name(cpu_name);
+ cpu_id = cpu_get_cpuid();
+
+ /* Look for string to match the name */
+ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
+ if (cpu_table[i].cpuid == cpu_id) {
+ cpu_type = cpu_table[i].name;
+ break;
+ }
+ }
+
+ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
+ printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
+ cpu_id, cpu_type, get_current_microcode_rev());
+
+ cpu_feature_flag = cpu_get_feature_flags_ecx();
+ aes = !!(cpu_feature_flag & CPUID_AES);
+ txt = !!(cpu_feature_flag & CPUID_SMX);
+ vt = !!(cpu_feature_flag & CPUID_VMX);
+ printk(BIOS_DEBUG,
+ "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
+ mode[aes], mode[txt], mode[vt]);
+}
+
+static void report_mch_info(void)
+{
+ int i;
+ pci_devfn_t dev = PCI_DEV_ROOT;
+ uint16_t mchid = get_dev_id(dev);
+ const char *mch_type = "Unknown";
+
+ for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
+ if (mch_table[i].mchid == mchid) {
+ mch_type = mch_table[i].name;
+ break;
+ }
+ }
+
+ printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
+ mchid, get_dev_revision(dev), mch_type);
+}
+
+static void report_pch_info(void)
+{
+ int i;
+ pci_devfn_t dev = PCI_DEV_ESPI;
+ uint16_t espiid = get_dev_id(dev);
+ const char *pch_type = "Unknown";
+
+ for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
+ if (pch_table[i].espiid == espiid) {
+ pch_type = pch_table[i].name;
+ break;
+ }
+ }
+ printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
+ espiid, get_dev_revision(dev), pch_type);
+}
+
+static void report_igd_info(void)
+{
+ int i;
+ pci_devfn_t dev = PCI_DEV_IGD;
+ uint16_t igdid = get_dev_id(dev);
+ const char *igd_type = "Unknown";
+
+ for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
+ if (igd_table[i].igdid == igdid) {
+ igd_type = igd_table[i].name;
+ break;
+ }
+ }
+ printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
+ igdid, get_dev_revision(dev), igd_type);
+}
+
+void report_platform_info(void)
+{
+ report_cpu_info();
+ report_mch_info();
+ report_pch_info();
+ report_igd_info();
+}
diff --git a/src/soc/intel/meteorlake/bootblock/soc_die.c b/src/soc/intel/meteorlake/bootblock/soc_die.c
new file mode 100644
index 0000000..b852e10
--- /dev/null
+++ b/src/soc/intel/meteorlake/bootblock/soc_die.c
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <device/device.h>
+#include <device/pci_ops.h>
+#include <intelblocks/fast_spi.h>
+#include <intelblocks/gspi.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/p2sb.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/rtc.h>
+#include <intelblocks/systemagent.h>
+#include <intelblocks/tco.h>
+#include <intelblocks/uart.h>
+#include <soc/bootblock.h>
+#include <soc/espi.h>
+#include <soc/iomap.h>
+#include <soc/p2sb.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+
+#define PCR_PSF8_TO_SHDW_PMC_REG_BASE 0xA00
+#define PCR_PSFX_TO_SHDW_BAR0 0
+#define PCR_PSFX_TO_SHDW_BAR1 0x4
+#define PCR_PSFX_TO_SHDW_BAR2 0x8
+#define PCR_PSFX_TO_SHDW_BAR3 0xC
+#define PCR_PSFX_TO_SHDW_BAR4 0x10
+#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
+#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
+
+#define PCR_DMI_ACPIBA 0x27B4
+#define PCR_DMI_ACPIBDID 0x27B8
+#define PCR_DMI_PMBASEA 0x27AC
+#define PCR_DMI_PMBASEC 0x27B0
+
+static void soc_die_config_pwrmbase(void)
+{
+ /*
+ * Assign Resources to PWRMBASE
+ * Clear BIT 1-2 Command Register
+ */
+ pci_and_config16(PCI_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
+
+ /* Program PWRM Base */
+ pci_write_config32(PCI_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
+
+ /* Enable Bus Master and MMIO Space */
+ pci_or_config16(PCI_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
+
+ /* Enable PWRM in PMC */
+ setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
+}
+
+static void soc_die_early_iorange_init(void)
+{
+ uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
+ LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
+
+ /* IO Decode Range */
+ if (CONFIG(DRIVERS_UART_8250IO))
+ lpc_io_setup_comm_a_b();
+
+ /* IO Decode Enable */
+ lpc_enable_fixed_io_ranges(io_enables);
+
+ /* Program generic IO Decode Range */
+ pch_enable_lpc();
+}
+
+void bootblock_soc_die_early_init(void)
+{
+ const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
+ { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
+ };
+
+ bootblock_systemagent_early_init();
+
+ /* Enable MCHBAR early, needed by IOC driver */
+ sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources));
+
+ fast_spi_cache_bios_region();
+ soc_die_early_iorange_init();
+ if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
+ uart_bootblock_init();
+
+ /*
+ * Perform P2SB configuration before any another controller initialization as the
+ * controller might want to perform PCR settings.
+ */
+ p2sb_enable_bar();
+ p2sb_configure_hpet();
+
+ fast_spi_early_init(SPI_BASE_ADDRESS);
+ gspi_early_bar_init();
+
+ /*
+ * Enabling SoC PMC PWRM Base for accessing
+ * Global Reset Cause Register.
+ */
+ soc_die_config_pwrmbase();
+}
+
+static void soc_die_config_acpibase(void)
+{
+ uint32_t pmc_reg_value;
+ uint32_t pmc_base_reg = PCR_PSF8_TO_SHDW_PMC_REG_BASE;
+
+ pmc_reg_value = pcr_read32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
+
+ if (pmc_reg_value != 0xffffffff) {
+ /* Disable Io Space before changing the address */
+ pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
+ ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
+ /* Program ABASE in PSF3 PMC space BAR4 */
+ pcr_write32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
+ ACPI_BASE_ADDRESS);
+ /* Enable IO Space */
+ pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
+ ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
+ }
+}
+
+void bootblock_soc_die_init(void)
+{
+ /*
+ * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
+ * GPE0_STS, GPE0_EN registers.
+ */
+ soc_die_config_acpibase();
+
+ /* Set up GPE configuration */
+ pmc_gpe_init();
+
+ enable_rtc_upper_bank();
+
+ /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
+ tco_configure();
+}
diff --git a/src/soc/intel/meteorlake/include/soc/bootblock.h b/src/soc/intel/meteorlake/include/soc/bootblock.h
new file mode 100644
index 0000000..f36c056
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/bootblock.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_METEORLAKE_BOOTBLOCK_H_
+#define _SOC_METEORLAKE_BOOTBLOCK_H_
+
+/* Bootblock pre console init programming */
+void bootblock_soc_die_early_init(void);
+void bootblock_ioe_die_early_init(void);
+
+/* Bootblock post console init programming */
+void bootblock_soc_die_init(void);
+void report_platform_info(void);
+
+#endif
diff --git a/src/soc/intel/meteorlake/include/soc/espi.h b/src/soc/intel/meteorlake/include/soc/espi.h
new file mode 100644
index 0000000..0b03cba
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/espi.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_METEORLAKE_ESPI_H_
+#define _SOC_METEORLAKE_ESPI_H_
+
+/* PCI Configuration Space (D31:F0): ESPI */
+#define SCI_IRQ_SEL (7 << 0)
+#define SCIS_IRQ9 0
+#define SCIS_IRQ10 1
+#define SCIS_IRQ11 2
+#define SCIS_IRQ20 4
+#define SCIS_IRQ21 5
+#define SCIS_IRQ22 6
+#define SCIS_IRQ23 7
+#define SERIRQ_CNTL 0x64
+#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */
+#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1 */
+#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2 */
+#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */
+#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */
+#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */
+#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */
+#define LGMR 0x98 /* ESPI Generic Memory Range */
+#define PCCTL 0xE0 /* PCI Clock Control */
+#define CLKRUN_EN (1 << 0)
+
+#endif
diff --git a/src/soc/intel/meteorlake/include/soc/iomap.h b/src/soc/intel/meteorlake/include/soc/iomap.h
new file mode 100644
index 0000000..c50fdb2
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/iomap.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_METEORLAKE_IOMAP_H_
+#define _SOC_METEORLAKE_IOMAP_H_
+
+#include <soc/pcr_ids.h>
+
+/*
+ * Memory-mapped I/O registers.
+ */
+#define PCH_PRESERVED_BASE_ADDRESS 0xfd800000
+#define PCH_PRESERVED_BASE_SIZE 0x01000000
+
+#define MCH_BASE_ADDRESS 0xfedc0000
+#define MCH_BASE_SIZE 0x20000
+
+#define DMI_BASE_ADDRESS 0xfeda0000
+#define DMI_BASE_SIZE 0x1000
+
+#define EP_BASE_ADDRESS 0xfeda1000
+#define EP_BASE_SIZE 0x1000
+
+#define EDRAM_BASE_ADDRESS 0xfed80000
+#define EDRAM_BASE_SIZE 0x4000
+
+#define HPET_BASE_ADDRESS 0xfed00000
+
+#define PCH_PWRM_BASE_ADDRESS 0xfe000000
+#define PCH_PWRM_BASE_SIZE 0x10000
+
+#define GPIO_BASE_SIZE 0x10000
+
+#define HECI1_BASE_ADDRESS 0xfeda2000
+
+#define VTD_BASE_ADDRESS 0xfc800000
+#define VTD_BASE_SIZE 0x00002000
+
+#define GFXVT_BASE_ADDRESS 0xfc800000
+#define GFXVT_BASE_SIZE 0x1000
+
+#define VTVC0_BASE_ADDRESS 0xfc801000
+#define VTVC0_BASE_SIZE 0x1000
+
+#define UART_BASE_SIZE 0x1000
+#define UART_BASE_0_ADDRESS 0xfe03e000
+/* Both UART BAR 0 and 1 are 4KB in size */
+#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \
+ UART_BASE_SIZE * (x)))
+#define UART_BASE(x) UART_BASE_0_ADDR(x)
+
+#define EARLY_GSPI_BASE_ADDRESS 0xfe030000
+
+#define EARLY_I2C_BASE_ADDRESS 0xfe020000
+#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
+
+#define SPI_BASE_ADDRESS 0xfe010000
+
+#define REG_BASE_ADDRESS 0xd0000000
+#define REG_BASE_SIZE (256 * MiB)
+
+#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
+#define P2SB_SIZE (16 * MiB)
+
+/*
+ * I/O port address space
+ */
+#define ACPI_BASE_ADDRESS 0x1800
+#define ACPI_BASE_SIZE 0x100
+
+#define TCO_BASE_ADDRESS 0x400
+#define TCO_BASE_SIZE 0x20
+#endif
diff --git a/src/soc/intel/meteorlake/include/soc/p2sb.h b/src/soc/intel/meteorlake/include/soc/p2sb.h
new file mode 100644
index 0000000..c515475
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/p2sb.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_METEORLAKE_P2SB_H_
+#define _SOC_METEORLAKE_P2SB_H_
+
+#define HPTC_OFFSET 0x60
+#define HPTC_ADDR_ENABLE_BIT (1 << 7)
+
+#define PCH_P2SB_EPMASK0 0x220
+
+#endif
diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h
new file mode 100644
index 0000000..4d0e343
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h
@@ -0,0 +1,233 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_METEORLAKE_PCI_DEVS_H_
+#define _SOC_METEORLAKE_PCI_DEVS_H_
+
+#include <device/pci_def.h>
+
+#define _PCI_DEVFN(slot, func) PCI_DEVFN(PCI_DEV_SLOT_ ## slot, func)
+#if !defined(__SIMPLE_DEVICE__)
+#include <device/device.h>
+#define _PCI_DEV(slot, func) pcidev_path_on_root(_PCI_DEVFN(slot, func), __func__)
+#else
+#define _PCI_DEV(slot, func) PCI_DEV(0, PCI_DEV_SLOT_ ## slot, func)
+#endif
+
+/* System Agent Devices */
+#define PCI_DEV_SLOT_ROOT 0x00
+#define PCI_DEVFN_ROOT _PCI_DEVFN(ROOT, 0)
+#if defined(__SIMPLE_DEVICE__)
+#define PCI_DEV_ROOT _PCI_DEV(ROOT, 0)
+#endif
+
+#define PCI_DEV_SLOT_PCIE_3 0x1
+#define PCI_DEVFN_PCIE12 _PCI_DEVFN(PCIE_3, 0)
+#define PCI_DEV_PCIE12 _PCI_DEV(PCIE_3, 0)
+
+#define PCI_DEV_SLOT_IGD 0x02
+#define PCI_DEVFN_IGD _PCI_DEVFN(IGD, 0)
+#define PCI_DEV_IGD _PCI_DEV(IGD, 0)
+
+#define PCI_DEV_SLOT_DPTF 0x04
+#define PCI_DEVFN_DPTF _PCI_DEVFN(DPTF, 0)
+#define PCI_DEV_DPTF _PCI_DEV(DPTF, 0)
+
+#define PCI_DEV_SLOT_IPU 0x05
+#define PCI_DEVFN_IPU _PCI_DEVFN(IPU, 0)
+#define PCI_DEV_IPU _PCI_DEV(IPU, 0)
+
+#define PCI_DEV_SLOT_PCIE_2 0x6
+#define PCI_DEVFN_PCIE9 _PCI_DEVFN(PCIE_2, 0)
+#define PCI_DEVFN_PCIE10 _PCI_DEVFN(PCIE_2, 1)
+#define PCI_DEVFN_PCIE11 _PCI_DEVFN(PCIE_2, 2)
+#define PCI_DEV_PCIE9 _PCI_DEV(PCIE_2, 0)
+#define PCI_DEV_PCIE10 _PCI_DEV(PCIE_2, 1)
+#define PCI_DEV_PCIE11 _PCI_DEV(PCIE_2, 2)
+
+#define PCI_DEV_SLOT_TBT 0x07
+#define PCI_DEVFN_TBT(x) _PCI_DEVFN(TBT, (x))
+#define NUM_TBT_FUNCTIONS 4
+#define PCI_DEVFN_TBT0 _PCI_DEVFN(TBT, 0)
+#define PCI_DEVFN_TBT1 _PCI_DEVFN(TBT, 1)
+#define PCI_DEVFN_TBT2 _PCI_DEVFN(TBT, 2)
+#define PCI_DEVFN_TBT3 _PCI_DEVFN(TBT, 3)
+#define PCI_DEV_TBT0 _PCI_DEV(TBT, 0)
+#define PCI_DEV_TBT1 _PCI_DEV(TBT, 1)
+#define PCI_DEV_TBT2 _PCI_DEV(TBT, 2)
+#define PCI_DEV_TBT3 _PCI_DEV(TBT, 3)
+
+#define PCI_DEV_SLOT_GNA 0x08
+#define PCI_DEVFN_GNA _PCI_DEVFN(GNA, 0)
+#define PCI_DEV_GNA _PCI_DEV(GNA, 0)
+
+#define PCI_DEV_SLOT_TCSS 0x0d
+#define NUM_TCSS_DMA_FUNCTIONS 2
+#define PCI_DEVFN_TCSS_DMA(x) _PCI_DEVFN(TCSS, ((x) + 2))
+#define PCI_DEVFN_TCSS_XHCI _PCI_DEVFN(TCSS, 0)
+#define PCI_DEVFN_TCSS_XDCI _PCI_DEVFN(TCSS, 1)
+#define PCI_DEVFN_TCSS_DMA0 _PCI_DEVFN(TCSS, 2)
+#define PCI_DEVFN_TCSS_DMA1 _PCI_DEVFN(TCSS, 3)
+#define PCI_DEV_TCSS_XHCI _PCI_DEV(TCSS, 0)
+#define PCI_DEV_TCSS_XDCI _PCI_DEV(TCSS, 1)
+#define PCI_DEV_TCSS_DMA0 _PCI_DEV(TCSS, 2)
+#define PCI_DEV_TCSS_DMA1 _PCI_DEV(TCSS, 3)
+
+#define PCI_DEV_SLOT_VMD 0x0e
+#define PCI_DEVFN_VMD _PCI_DEVFN(VMD, 0)
+#define PCI_DEV_VMD _PCI_DEV(VMD, 0)
+
+#define PCI_DEV_SLOT_THC 0x10
+#define PCI_DEVFN_THC0 _PCI_DEVFN(THC, 0)
+#define PCI_DEVFN_THC1 _PCI_DEVFN(THC, 1)
+#define PCI_DEV_THC0 _PCI_DEV(THC, 0)
+#define PCI_DEV_THC1 _PCI_DEV(THC, 1)
+
+#define PCI_DEV_SLOT_ISH 0x12
+#define PCI_DEVFN_ISH _PCI_DEVFN(ISH, 0)
+#define PCI_DEVFN_UFS _PCI_DEVFN(ISH, 7)
+#define PCI_DEV_ISH _PCI_DEV(ISH, 0)
+#define PCI_DEV_UFS _PCI_DEV(ISH, 7)
+
+#define PCI_DEV_SLOT_IOE 0x13
+#define PCI_DEVFN_IOE_P2SB _PCI_DEVFN(IOE, 0)
+#define PCI_DEVFN_IOE_PMC _PCI_DEVFN(IOE, 2)
+#define PCI_DEVFN_IOE_SRAM _PCI_DEVFN(IOE, 3)
+#define PCI_DEV_IOE_P2SB _PCI_DEV(IOE, 0)
+#define PCI_DEV_IOE_PMC _PCI_DEV(IOE, 2)
+#define PCI_DEV_IOE_SRAM _PCI_DEV(IOE, 3)
+
+#define PCI_DEV_SLOT_XHCI 0x14
+#define PCI_DEVFN_XHCI _PCI_DEVFN(XHCI, 0)
+#define PCI_DEVFN_USBOTG _PCI_DEVFN(XHCI, 1)
+#define PCI_DEVFN_SRAM _PCI_DEVFN(XHCI, 2)
+#define PCI_DEVFN_CNVI_WIFI _PCI_DEVFN(XHCI, 3)
+#define PCI_DEV_XHCI _PCI_DEV(XHCI, 0)
+#define PCI_DEV_USBOTG _PCI_DEV(XHCI, 1)
+#define PCI_DEV_SRAM _PCI_DEV(XHCI, 2)
+#define PCI_DEV_CNVI_WIFI _PCI_DEV(XHCI, 3)
+
+#define PCI_DEV_SLOT_SIO0 0x15
+#define PCI_DEVFN_I2C0 _PCI_DEVFN(SIO0, 0)
+#define PCI_DEVFN_I2C1 _PCI_DEVFN(SIO0, 1)
+#define PCI_DEVFN_I2C2 _PCI_DEVFN(SIO0, 2)
+#define PCI_DEVFN_I2C3 _PCI_DEVFN(SIO0, 3)
+#define PCI_DEV_I2C0 _PCI_DEV(SIO0, 0)
+#define PCI_DEV_I2C1 _PCI_DEV(SIO0, 1)
+#define PCI_DEV_I2C2 _PCI_DEV(SIO0, 2)
+#define PCI_DEV_I2C3 _PCI_DEV(SIO0, 3)
+
+#define PCI_DEV_SLOT_CSE 0x16
+#define PCI_DEVFN_CSE _PCI_DEVFN(CSE, 0)
+#define PCI_DEVFN_CSE_2 _PCI_DEVFN(CSE, 1)
+#define PCI_DEVFN_CSE_IDER _PCI_DEVFN(CSE, 2)
+#define PCI_DEVFN_CSE_KT _PCI_DEVFN(CSE, 3)
+#define PCI_DEVFN_CSE_3 _PCI_DEVFN(CSE, 4)
+#define PCI_DEVFN_CSE_4 _PCI_DEVFN(CSE, 5)
+#define PCI_DEV_CSE _PCI_DEV(CSE, 0)
+#define PCI_DEV_CSE_2 _PCI_DEV(CSE, 1)
+#define PCI_DEV_CSE_IDER _PCI_DEV(CSE, 2)
+#define PCI_DEV_CSE_KT _PCI_DEV(CSE, 3)
+#define PCI_DEV_CSE_3 _PCI_DEV(CSE, 4)
+#define PCI_DEV_CSE_4 _PCI_DEV(CSE, 5)
+
+#define PCI_DEV_SLOT_SATA 0x17
+#define PCI_DEVFN_SATA _PCI_DEVFN(SATA, 0)
+#define PCI_DEV_SATA _PCI_DEV(SATA, 0)
+
+#define PCI_DEV_SLOT_ESE 0x18
+#define PCI_DEVFN_ESE1 _PCI_DEVFN(ESE, 0)
+#define PCI_DEVFN_ESE2 _PCI_DEVFN(ESE, 1)
+#define PCI_DEVFN_ESE3 _PCI_DEVFN(ESE, 2)
+#define PCI_DEV_ESE1 _PCI_DEV(ESE, 0)
+#define PCI_DEV_ESE2 _PCI_DEV(ESE, 1)
+#define PCI_DEV_ESE3 _PCI_DEV(ESE, 2)
+
+#define PCI_DEV_SLOT_SIO1 0x19
+#define PCI_DEVFN_I2C4 _PCI_DEVFN(SIO1, 0)
+#define PCI_DEVFN_I2C5 _PCI_DEVFN(SIO1, 1)
+#define PCI_DEVFN_UART2 _PCI_DEVFN(SIO1, 2)
+#define PCI_DEV_I2C4 _PCI_DEV(SIO1, 0)
+#define PCI_DEV_I2C5 _PCI_DEV(SIO1, 1)
+#define PCI_DEV_UART2 _PCI_DEV(SIO1, 2)
+
+#define PCI_DEV_SLOT_PCIE_1 0x1c
+#define PCI_DEVFN_PCIE1 _PCI_DEVFN(PCIE_1, 0)
+#define PCI_DEVFN_PCIE2 _PCI_DEVFN(PCIE_1, 1)
+#define PCI_DEVFN_PCIE3 _PCI_DEVFN(PCIE_1, 2)
+#define PCI_DEVFN_PCIE4 _PCI_DEVFN(PCIE_1, 3)
+#define PCI_DEVFN_PCIE5 _PCI_DEVFN(PCIE_1, 4)
+#define PCI_DEVFN_PCIE6 _PCI_DEVFN(PCIE_1, 5)
+#define PCI_DEVFN_PCIE7 _PCI_DEVFN(PCIE_1, 6)
+#define PCI_DEVFN_PCIE8 _PCI_DEVFN(PCIE_1, 7)
+#define PCI_DEV_PCIE1 _PCI_DEV(PCIE_1, 0)
+#define PCI_DEV_PCIE2 _PCI_DEV(PCIE_1, 1)
+#define PCI_DEV_PCIE3 _PCI_DEV(PCIE_1, 2)
+#define PCI_DEV_PCIE4 _PCI_DEV(PCIE_1, 3)
+#define PCI_DEV_PCIE5 _PCI_DEV(PCIE_1, 4)
+#define PCI_DEV_PCIE6 _PCI_DEV(PCIE_1, 5)
+#define PCI_DEV_PCIE7 _PCI_DEV(PCIE_1, 6)
+#define PCI_DEV_PCIE8 _PCI_DEV(PCIE_1, 7)
+
+#define PCI_DEV_SLOT_SIO2 0x1e
+#define PCI_DEVFN_UART0 _PCI_DEVFN(SIO2, 0)
+#define PCI_DEVFN_UART1 _PCI_DEVFN(SIO2, 1)
+#define PCI_DEVFN_GSPI0 _PCI_DEVFN(SIO2, 2)
+#define PCI_DEVFN_GSPI1 _PCI_DEVFN(SIO2, 3)
+#define PCI_DEVFN_TSN1 _PCI_DEVFN(SIO2, 4)
+#define PCI_DEVFN_TSN2 _PCI_DEVFN(SIO2, 5)
+#define PCI_DEV_UART0 _PCI_DEV(SIO2, 0)
+#define PCI_DEV_UART1 _PCI_DEV(SIO2, 1)
+#define PCI_DEV_GSPI0 _PCI_DEV(SIO2, 2)
+#define PCI_DEV_GSPI1 _PCI_DEV(SIO2, 3)
+#define PCI_DEV_TSN1 _PCI_DEV(SIO2, 4)
+#define PCI_DEV_TSN2 _PCI_DEV(SIO2, 5)
+
+#define PCI_DEV_SLOT_ESPI 0x1f
+#define PCI_DEVFN_ESPI _PCI_DEVFN(ESPI, 0)
+#define PCI_DEVFN_P2SB _PCI_DEVFN(ESPI, 1)
+#define PCI_DEVFN_PMC _PCI_DEVFN(ESPI, 2)
+#define PCI_DEVFN_HDA _PCI_DEVFN(ESPI, 3)
+#define PCI_DEVFN_SMBUS _PCI_DEVFN(ESPI, 4)
+#define PCI_DEVFN_SPI _PCI_DEVFN(ESPI, 5)
+#define PCI_DEVFN_GBE _PCI_DEVFN(ESPI, 6)
+#define PCI_DEVFN_NPK _PCI_DEVFN(ESPI, 7)
+#define PCI_DEV_ESPI _PCI_DEV(ESPI, 0)
+#define PCI_DEV_P2SB _PCI_DEV(ESPI, 1)
+
+#if !ENV_RAMSTAGE
+/*
+ * PCI_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets
+ * hidden from PCI bus after call to FSP-S. This leads to resource allocator
+ * dropping it from the root bus as unused device. All references to PCI_DEV_PMC
+ * would then return NULL and can go unnoticed if not handled properly. Since,
+ * this device does not have any special chip config associated with it, it is
+ * okay to not provide the definition for it in ramstage.
+ */
+#define PCI_DEV_PMC _PCI_DEV(ESPI, 2)
+#endif
+
+#define PCI_DEV_HDA _PCI_DEV(ESPI, 3)
+#define PCI_DEV_SMBUS _PCI_DEV(ESPI, 4)
+#define PCI_DEV_SPI _PCI_DEV(ESPI, 5)
+#define PCI_DEV_GBE _PCI_DEV(ESPI, 6)
+#define PCI_DEV_NPK _PCI_DEV(ESPI, 7)
+
+#endif
+
+/* for common code */
+#define PCH_DEV_SLOT_CSE PCI_DEV_SLOT_CSE
+#define PCH_DEVFN_CSE PCI_DEVFN_CSE
+#define PCH_DEV_CSE PCI_DEV_CSE
+#define PCH_DEV_SPI PCI_DEV_SPI
+#define PCH_DEV_LPC PCI_DEV_ESPI
+#define PCH_DEV_P2SB PCI_DEV_P2SB
+#define PCH_DEV_SMBUS PCI_DEV_SMBUS
+#define PCH_DEV_XHCI PCI_DEV_XHCI
+#define PCH_DEVFN_XHCI PCI_DEVFN_XHCI
+#define PCH_DEVFN_PMC PCI_DEVFN_PMC
+#define PCH_DEV_SLOT_ISH PCI_DEV_SLOT_ISH
+#define SA_DEV_ROOT PCI_DEV_ROOT
+#define SA_DEVFN_ROOT PCI_DEVFN_ROOT
+#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN_TCSS_DMA0
+#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN_TCSS_DMA1
+#define SA_DEVFN_IGD PCI_DEVFN_IGD
diff --git a/src/soc/intel/meteorlake/include/soc/pcr_ids.h b/src/soc/intel/meteorlake/include/soc/pcr_ids.h
new file mode 100644
index 0000000..0ef9f30
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/pcr_ids.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_METEORLAKE_PCR_H
+#define SOC_METEORLAKE_PCR_H
+
+/*
+ * Port ids
+ */
+
+#define PID_GPIOCOM0 0xD1
+#define PID_GPIOCOM1 0xD2
+#define PID_GPIOCOM3 0xD3
+#define PID_GPIOCOM4 0xD4
+#define PID_GPIOCOM5 0xD5
+
+#define PID_PSF8 0x08
+#define PID_PSF7 0x07
+#define PID_PSF6 0x06
+#define PID_PSF5 0x8F
+#define PID_PSF4 0xBD
+#define PID_PSF3 0xBC
+#define PID_PSF2 0xBB
+#define PID_PSF1 0xBA
+#define PID_CSME0 0xC6
+#define PID_PSTH 0x6A
+#define PID_ITSS 0xCA
+#define PID_RTC 0x6C
+#define PID_ISCLK 0x64
+#define PID_DMI 0x88
+#define PID_IOM 0xAA
+
+#endif
diff --git a/src/soc/intel/meteorlake/include/soc/pm.h b/src/soc/intel/meteorlake/include/soc/pm.h
new file mode 100644
index 0000000..c486232
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/pm.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PM_H_
+#define _SOC_PM_H_
+
+#define PM1_STS 0x00
+#define WAK_STS (1 << 15)
+#define PCIEXPWAK_STS (1 << 14)
+#define PRBTNOR_STS (1 << 11)
+#define RTC_STS (1 << 10)
+#define PWRBTN_STS (1 << 8)
+#define GBL_STS (1 << 5)
+#define BM_STS (1 << 4)
+#define TMROF_STS (1 << 0)
+#define PM1_EN 0x02
+#define PCIEXPWAK_DIS (1 << 14)
+#define RTC_EN (1 << 10)
+#define PWRBTN_EN (1 << 8)
+#define GBL_EN (1 << 5)
+#define TMROF_EN (1 << 0)
+#define PM1_CNT 0x04
+#define GBL_RLS (1 << 2)
+#define BM_RLD (1 << 1)
+#define SCI_EN (1 << 0)
+#define PM1_TMR 0x08
+#define SMI_EN 0x30
+#define XHCI_SMI_EN (1 << 31)
+#define ME_SMI_EN (1 << 30)
+#define ESPI_SMI_EN (1 << 28)
+#define GPIO_UNLOCK_SMI_EN (1 << 27)
+#define INTEL_USB2_EN (1 << 18)
+#define LEGACY_USB2_EN (1 << 17)
+#define PERIODIC_EN (1 << 14)
+#define TCO_SMI_EN (1 << 13)
+#define MCSMI_EN (1 << 11)
+#define BIOS_RLS (1 << 7)
+#define SWSMI_TMR_EN (1 << 6)
+#define APMC_EN (1 << 5)
+#define SLP_SMI_EN (1 << 4)
+#define LEGACY_USB_EN (1 << 3)
+#define BIOS_EN (1 << 2)
+#define EOS (1 << 1)
+#define GBL_SMI_EN (1 << 0)
+#define SMI_STS 0x34
+#define SMI_STS_BITS 32
+#define XHCI_SMI_STS_BIT 31
+#define ME_SMI_STS_BIT 30
+#define ESPI_SMI_STS_BIT 28
+#define GPIO_UNLOCK_SMI_STS_BIT 27
+#define SPI_SMI_STS_BIT 26
+#define SCC_SMI_STS_BIT 25
+#define MONITOR_STS_BIT 21
+#define PCI_EXP_SMI_STS_BIT 20
+#define SMBUS_SMI_STS_BIT 16
+#define SERIRQ_SMI_STS_BIT 15
+#define PERIODIC_STS_BIT 14
+#define TCO_STS_BIT 13
+#define DEVMON_STS_BIT 12
+#define MCSMI_STS_BIT 11
+#define GPIO_STS_BIT 10
+#define GPE0_STS_BIT 9
+#define PM1_STS_BIT 8
+#define SWSMI_TMR_STS_BIT 6
+#define APM_STS_BIT 5
+#define SMI_ON_SLP_EN_STS_BIT 4
+#define LEGACY_USB_STS_BIT 3
+#define BIOS_STS_BIT 2
+#define GPE_CNTL 0x42
+#define SWGPE_CTRL (1 << 1)
+#define DEVACT_STS 0x44
+#define PM2_CNT 0x50
+
+#define GPE0_REG_MAX 4
+#define GPE0_REG_SIZE 32
+#define GPE0_STS(x) (0x60 + ((x) * 4))
+#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */
+#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */
+#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */
+#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */
+#define GPE_STS_RSVD GPE_STD
+#define WADT_STS (1 << 18)
+#define GPIO_T2_STS (1 << 15)
+#define ESPI_STS (1 << 14)
+#define PME_B0_STS (1 << 13)
+#define ME_SCI_STS (1 << 12)
+#define PME_STS (1 << 11)
+#define BATLOW_STS (1 << 10)
+#define PCI_EXP_STS (1 << 9)
+#define SMB_WAK_STS (1 << 7)
+#define TCOSCI_STS (1 << 6)
+#define SWGPE_STS (1 << 2)
+#define HOT_PLUG_STS (1 << 1)
+#define GPE0_EN(x) (0x70 + ((x) * 4))
+#define WADT_EN (1 << 18)
+#define GPIO_T2_EN (1 << 15)
+#define ESPI_EN (1 << 14)
+#define PME_B0_EN_BIT 13
+#define PME_B0_EN (1 << PME_B0_EN_BIT)
+#define ME_SCI_EN (1 << 12)
+#define PME_EN (1 << 11)
+#define BATLOW_EN (1 << 10)
+#define PCI_EXP_EN (1 << 9)
+#define TCOSCI_EN (1 << 6)
+#define SWGPE_EN (1 << 2)
+#define HOT_PLUG_EN (1 << 1)
+
+#define EN_BLOCK 3
+
+/*
+ * Enable SMI generation:
+ * - on APMC writes (io 0xb2)
+ * - on writes to SLP_EN (sleep states)
+ * - on writes to GBL_RLS (bios commands)
+ * - on eSPI events (does nothing on LPC systems)
+ * No SMIs:
+ * - on TCO events, unless enabled in common code
+ * - on microcontroller writes (io 0x62/0x66)
+ */
+#define ENABLE_SMI_PARAMS \
+ (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
+
+#define PSS_RATIO_STEP 2
+#define PSS_MAX_ENTRIES 8
+#define PSS_LATENCY_TRANSITION 10
+#define PSS_LATENCY_BUSMASTER 10
+
+#if !defined(__ACPI__)
+
+#include <acpi/acpi.h>
+#include <soc/gpe.h>
+#include <soc/iomap.h>
+#include <soc/smbus.h>
+#include <soc/pmc.h>
+
+struct chipset_power_state {
+ uint16_t pm1_sts;
+ uint16_t pm1_en;
+ uint32_t pm1_cnt;
+ uint16_t tco1_sts;
+ uint16_t tco2_sts;
+ uint32_t gpe0_sts[4];
+ uint32_t gpe0_en[4];
+ uint32_t gen_pmcon_a;
+ uint32_t gen_pmcon_b;
+ uint32_t gblrst_cause[2];
+ uint32_t hpr_cause0;
+ uint32_t prev_sleep_state;
+} __packed;
+
+/* Get base address PMC memory mapped registers. */
+uint8_t *pmc_mmio_regs(void);
+
+/* Get base address of TCO I/O registers. */
+uint16_t smbus_tco_regs(void);
+
+/* Set the DISB after DRAM init */
+void pmc_set_disb(void);
+
+/* STM Support */
+uint16_t get_pmbase(void);
+#endif /* !defined(__ACPI__) */
+#endif
diff --git a/src/soc/intel/meteorlake/include/soc/smbus.h b/src/soc/intel/meteorlake/include/soc/smbus.h
new file mode 100644
index 0000000..c865fbe
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/smbus.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_SMBUS_H_
+#define _SOC_SMBUS_H_
+
+#include <intelpch/smbus.h>
+
+#endif