commit b7b1b2884fb901ac61b7fde6729f811b2e56dd3e
author Patrick Rudolph <siro@das-labor.org> Tue Jun 14 18:44:28 2016 +0200
committer Martin Roth <martinroth@google.com> Mon Jun 20 21:44:50 2016 +0200
tree 6f1633379349ebd4cd60299596074635d71f39bc
parent 7bddd30e948e6c3856336e77221fdbe5ba749453

nb/intel/sandybridge/raminit: Do code cleanup

Simplify calculation of value.

Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).

Change-Id: I3ecd12c431b46a8d2218f33d7eb3e10de3bcd61d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15181
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/northbridge/intel/sandybridge/raminit.c

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 15590d1..abb7ceb 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -657,7 +657,6 @@
 		ctrl->timC_offset[1] = 7;
 		ctrl->timC_offset[2] = 7;
 		ctrl->reg_c14_offset = 16;
-		ctrl->reg_5064b0 = 0x218;
 		ctrl->reg_320c_range_threshold = 13;
 	} else if (ctrl->tCK <= TCK_933MHZ) {
 		ctrl->tCK = TCK_933MHZ;
@@ -668,7 +667,6 @@
 		ctrl->timC_offset[1] = 6;
 		ctrl->timC_offset[2] = 6;
 		ctrl->reg_c14_offset = 14;
-		ctrl->reg_5064b0 = 0x1d5;
 		ctrl->reg_320c_range_threshold = 15;
 	} else if (ctrl->tCK <= TCK_800MHZ) {
 		ctrl->tCK = TCK_800MHZ;
@@ -679,7 +677,6 @@
 		ctrl->timC_offset[1] = 5;
 		ctrl->timC_offset[2] = 5;
 		ctrl->reg_c14_offset = 12;
-		ctrl->reg_5064b0 = 0x193;
 		ctrl->reg_320c_range_threshold = 15;
 	} else if (ctrl->tCK <= TCK_666MHZ) {
 		ctrl->tCK = TCK_666MHZ;
@@ -690,7 +687,6 @@
 		ctrl->timC_offset[1] = 4;
 		ctrl->timC_offset[2] = 4;
 		ctrl->reg_c14_offset = 10;
-		ctrl->reg_5064b0 = 0x150;
 		ctrl->reg_320c_range_threshold = 16;
 	} else if (ctrl->tCK <= TCK_533MHZ) {
 		ctrl->tCK = TCK_533MHZ;
@@ -701,7 +697,6 @@
 		ctrl->timC_offset[1] = 3;
 		ctrl->timC_offset[2] = 3;
 		ctrl->reg_c14_offset = 8;
-		ctrl->reg_5064b0 = 0x10d;
 		ctrl->reg_320c_range_threshold = 17;
 	} else  {
 		ctrl->tCK = TCK_400MHZ;
@@ -712,10 +707,12 @@
 		ctrl->timC_offset[1] = 2;
 		ctrl->timC_offset[2] = 2;
 		ctrl->reg_c14_offset = 8;
-		ctrl->reg_5064b0 = 0xcd;
 		ctrl->reg_320c_range_threshold = 17;
 	}
 
+	/* DLL_CONFIG_MDLL_W_TIMER */
+	ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3;
+
 	val32 = (1000 << 8) / ctrl->tCK;
 	printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32);