soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
This patch ensures coreboot is not publishing above 4GB mmio resource
if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size
is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff]
[ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff]
[ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref]
[ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff]
[ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff]
[ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref]
[ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index 589fcc1..89380aa 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -3,7 +3,7 @@
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,9 +17,6 @@
#include <soc/iomap.h>
-#define BASE_32GB 0x800000000
-#define SIZE_16GB 0x400000000
-
Name (_HID, EISAID ("PNP0A08")) /* PCIe */
Name (_CID, EISAID ("PNP0A03")) /* PCI */
@@ -214,20 +211,18 @@
Add (Subtract (PMAX, PMIN), 1, PLEN)
/* Patch PM02 range based on Memory Size */
- CreateQwordField (MCRS, PM02._MIN, MMIN)
- CreateQwordField (MCRS, PM02._MAX, MMAX)
- CreateQwordField (MCRS, PM02._LEN, MLEN)
-
- Store (\_SB.PCI0.MCHC.TUUD, Local0)
-
- If (LLessEqual (Local0, BASE_32GB)) {
- Store (BASE_32GB, MMIN)
- Store (SIZE_16GB, MLEN)
+ If (LEqual (A4GS, 0)) {
+ CreateQwordField (MCRS, PM02._LEN, MSEN)
+ Store (0, MSEN)
} Else {
- Store (0, MMIN)
- Store (0, MLEN)
+ CreateQwordField (MCRS, PM02._MIN, MMIN)
+ CreateQwordField (MCRS, PM02._MAX, MMAX)
+ CreateQwordField (MCRS, PM02._LEN, MLEN)
+ /* Set 64bit MMIO resource base and length */
+ Store (A4GS, MLEN)
+ Store (A4GB, MMIN)
+ Subtract (Add (MMIN, MLEN), 1, MMAX)
}
- Subtract (Add (MMIN, MLEN), 1, MMAX)
Return (MCRS)
}