tree edf35d12c3f0178f2d20aeeec89131ac235ec2f8
parent 88bbf166bc1856156b5b2f3f4767f9365dfd60c6
author Duncan Laurie <dlaurie@chromium.org> 1420579962 -0800
committer Stefan Reinauer <stefan.reinauer@coreboot.org> 1428689328 +0200

broadwell: Update SATA Gen3 TX adjustment registers

The registers that were used here are for CPT/PPT and not
for HSW/BDW chips.

Update this to update just the Gen3 TX Output Voltage Downscale
Amplitude Adjustment field in the SATA ECR T88.

BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus

Change-Id: I94b702dc4a3c98678ba048ff9cfa4a85cc5b1eed
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4c5816cc647b84266751e8a591eb85d7735fee12
Original-Change-Id: I98ec9678938a6675828721d5b57683077f555d21
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/238800
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9484
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>