commit | d0581315869331c4e934368cbb535692b486ebbc | [log] [tgz] |
---|---|---|
author | Patrick Rudolph <patrick.rudolph@9elements.com> | Fri May 01 18:31:48 2020 +0200 |
committer | Patrick Rudolph <siro@das-labor.org> | Tue Aug 11 05:14:01 2020 +0000 |
tree | 5ca9b74dc9b64d22e5f1b6e4672d24c2e225956f | |
parent | 173493784dd07ac1cbf055a0b26c55f9bd1f5a28 [diff] |
nb/intel/sandybridge/raminit: Add ECC debug code * Add ECC test code when DEBUG_RAM_SETUP is enabled * Move ECC scrubbing after set_scrambling_seed() to be able to observe what has been cleared in the test routine. If clearing happens before set_scrambling_seed the data is XORed with a different PRN. Data read from memory will look random instead of all zeros. * ECC scrubbing must happen after dram_dimm_set_mapping() The ECC logic is set to "normal mode" in dram_dimm_set_mapping(). In normal mode the ECC bits are calculated and stored on write transactions. * Move method out of try_init_dram_ddr3(). This satisfies point 2 and point 3 of the list above. Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.