commit b53858bacee1b3561ab0c70e3f82196f4e7eb6cb
author Benjamin Doron <benjamin.doron00@gmail.com> Mon Oct 12 04:19:42 2020 +0000
committer Nico Huber <nico.h@gmx.de> Fri Oct 16 22:03:34 2020 +0000
tree 71a05fe3201906f4ef52a81c0848a64ce994dbd2
parent 3f1de9add900305730a28be919a21a682ae6b224

soc/intel/skylake: Rename PcieRpAspm devicetree config

This configuration option shares a name with the FSP UPD, but
is enumerated differently. Change its name to minimise confusion
about the options.

Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/facebook/monolith/devicetree.cb

diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 95e2565..bb11d06 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -151,7 +151,7 @@
 	# Enable Advanced Error Reporting
 	register "PcieRpAdvancedErrorReporting[2]" = "1"
 	# Disable Aspm
-	register "PcieRpAspm[2]" = "AspmDisabled"
+	register "pcie_rp_aspm[2]" = "AspmDisabled"
 
 	# PCIE Port 4 disabled
 	# PCIE Port 5 x1 -> MODULE i219
@@ -166,7 +166,7 @@
 	# Enable Advanced Error Reporting
 	register "PcieRpAdvancedErrorReporting[5]" = "1"
 	# Disable Aspm
-	register "PcieRpAspm[5]" = "AspmDisabled"
+	register "pcie_rp_aspm[5]" = "AspmDisabled"
 
 	# PCIE Port 7 Disabled
 	# PCIE Port 8 Disabled
@@ -184,7 +184,7 @@
 	# Enable Advanced Error Reporting
 	register "PcieRpAdvancedErrorReporting[8]" = "1"
 	# Disable Aspm
-	register "PcieRpAspm[8]" = "AspmDisabled"
+	register "pcie_rp_aspm[8]" = "AspmDisabled"
 
 	# USB 2.0 Enable all ports
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB-C Port 2

src/soc/intel/skylake/chip.c

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 4139570..549f403 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -210,8 +210,8 @@
 	       sizeof(params->PcieRpHotPlug));
 	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
 		params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
-		if (config->PcieRpAspm[i])
-			params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1;
+		if (config->pcie_rp_aspm[i])
+			params->PcieRpAspm[i] = config->pcie_rp_aspm[i] - 1;
 		if (config->pcie_rp_l1substates[i])
 			params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1;
 	}

src/soc/intel/skylake/chip.h

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 5befb01..2584d5d 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -262,7 +262,7 @@
 		AspmL1,
 		AspmL0sL1,
 		AspmAutoConfig,
-	} PcieRpAspm[CONFIG_MAX_ROOT_PORTS];
+	} pcie_rp_aspm[CONFIG_MAX_ROOT_PORTS];
 
 	/* PCIe RP L1 substate */
 	enum {