tree 1e016479f41745936f40edbfe11d4a6d1405b1d5
parent 2d1dd5943d12a6ef46ab6d3d580545e89622e47d
author Subrata Banik <subrata.banik@intel.com> 1502707533 +0530
committer Aaron Durbin <adurbin@chromium.org> 1503684126 +0000

soc/intel/skylake: Move LPC lock down config after resource allocation

This patch to ensures that coreboot is performing LPC
registers lockdown after PCI enumeration is done.

This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.

coreboot has to change its execution order to meet those
requirements. Hence lpc register lock down has been moved
right after pci resource allocation is done, so that
lpc registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.

TEST=Ensure LPC register 0xDC bit 1 and 7 is set.

Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>