diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index cf6a907..109b6b5 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -3,9 +3,15 @@
 
 if CPU_INTEL_MODEL_206AX
 
+config ARCH_EXP_X86_64
+	bool "Experimental 64bit support"
+	depends on USE_NATIVE_RAMINIT
+	default n
+
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_ALL_STAGES_X86_32 if !ARCH_EXP_X86_64
+	select ARCH_ALL_STAGES_X86_64 if ARCH_EXP_X86_64
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select MMX
 	select SSE2
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 62a2139..4b5f2b3 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1509,9 +1509,12 @@
 {
 	unsigned int j;
 	unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64;
+	uintptr_t addr;
 
-	for (j = 0; j < 16; j++)
-		write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a);
+	for (j = 0; j < 16; j++) {
+		addr = 0x04000000 + channel_offset + 4 * j;
+		write32((void *)addr, j & 2 ? b : a);
+	}
 
 	sfence();
 
@@ -1531,13 +1534,16 @@
 	unsigned int j;
 	unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64;
 	unsigned int channel_step = 64 * num_of_channels(ctrl);
+	uintptr_t addr;
 
-	for (j = 0; j < 16; j++)
-		write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff);
-
-	for (j = 0; j < 16; j++)
-		write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0);
-
+	for (j = 0; j < 16; j++) {
+		addr = 0x04000000 + channel_offset + j * 4;
+		write32((void *)addr, 0xffffffff);
+	}
+	for (j = 0; j < 16; j++) {
+		addr = 0x04000000 + channel_offset + channel_step + j * 4;
+		write32((void *)addr, 0);
+	}
 	sfence();
 
 	program_wdb_pattern_length(channel, 16);
@@ -1929,6 +1935,7 @@
 	unsigned int i, j;
 	unsigned int offset = get_precedening_channels(ctrl, channel) * 64;
 	unsigned int step = 64 * num_of_channels(ctrl);
+	uintptr_t addr;
 
 	if (patno) {
 		u8 base8 = 0x80 >> ((patno - 1) % 8);
@@ -1940,14 +1947,16 @@
 				if (invert[patno - 1][i] & (1 << (j / 2)))
 					val = ~val;
 
-				write32((void *)((1 << 26) + offset + i * step + j * 4), val);
+				addr = (1 << 26) + offset + i * step + j * 4;
+				write32((void *)addr, val);
 			}
 		}
 	} else {
 		for (i = 0; i < ARRAY_SIZE(pattern); i++) {
 			for (j = 0; j < 16; j++) {
 				const u32 val = pattern[i][j];
-				write32((void *)((1 << 26) + offset + i * step + j * 4), val);
+				addr = (1 << 26) + offset + i * step + j * 4;
+				write32((void *)addr, val);
 			}
 		}
 		sfence();
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index dcb0bb4..1f14c42 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -165,7 +165,7 @@
 	// NOTE this will break as soon as the Azalia get's a bar above 4G.
 	// Is there anything we can do about it?
 	base = res2mmio(res, 0, 0);
-	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+	printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
 
 	if (RCBA32(CIR31) & (1 << 31)) {
 		reg32 = pci_read_config32(dev, 0x120);
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index c6b42ea..cc2eb28 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -258,18 +258,18 @@
 {
 	printk(BIOS_DEBUG, "CougarPoint PM init\n");
 	pci_write_config8(dev, 0xa9, 0x47);
-	RCBA32_AND_OR(CIR30, ~0UL, (1 << 6)|(1 << 0));
-	RCBA32_AND_OR(CIR5, ~0UL, (1 << 0));
-	RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14));
-	RCBA16_AND_OR(CIR2, ~0UL, (1 << 14));
+	RCBA32_AND_OR(CIR30, ~0U, (1 << 6)|(1 << 0));
+	RCBA32_AND_OR(CIR5, ~0U, (1 << 0));
+	RCBA16_AND_OR(CIR3, ~0U, (1 << 13)|(1 << 14));
+	RCBA16_AND_OR(CIR2, ~0U, (1 << 14));
 	RCBA32(DMC) = 0xc0388400;
-	RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18));
-	RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1));
+	RCBA32_AND_OR(CIR6, ~0U, (1 << 5)|(1 << 18));
+	RCBA32_AND_OR(CIR9, ~0U, (1 << 15)|(1 << 1));
 	RCBA32_AND_OR(CIR7, ~0x1f, 0xf);
 	RCBA32(PM_CFG) = 0x050f0000;
 	RCBA32(CIR8) = 0x04000000;
-	RCBA32_AND_OR(CIR10, ~0UL, 0xfffff);
-	RCBA32_AND_OR(CIR11, ~0UL, (1 << 1));
+	RCBA32_AND_OR(CIR10, ~0U, 0xfffff);
+	RCBA32_AND_OR(CIR11, ~0U, (1 << 1));
 	RCBA32(CIR12) = 0x0001c000;
 	RCBA32(CIR14) = 0x00061100;
 	RCBA32(CIR15) = 0x7f8fdfff;
@@ -371,10 +371,10 @@
 	reg16 |= (1 << 11);
 	pci_write_config16(dev, GEN_PMCON_1, reg16);
 
-	pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
-	pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
-	pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
-	pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
+	pch_iobp_update(0xEB007F07, ~0U, (1 << 31));
+	pch_iobp_update(0xEB004000, ~0U, (1 << 7));
+	pch_iobp_update(0xEC007F07, ~0U, (1 << 31));
+	pch_iobp_update(0xEC004000, ~0U, (1 << 7));
 
 	reg32 = RCBA32(CG);
 	reg32 |= (1 << 31);
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index c9bc14c..08a254f3 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -126,7 +126,7 @@
 		pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
 
 		/* Initialize AHCI memory-mapped space */
-		abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+		abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
 		printk(BIOS_DEBUG, "ABAR: %p\n", abar);
 		/* CAP (HBA Capabilities) : enable power management */
 		reg32 = read32(abar + 0x00);