diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index dcb0bb4..1f14c42 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -165,7 +165,7 @@
 	// NOTE this will break as soon as the Azalia get's a bar above 4G.
 	// Is there anything we can do about it?
 	base = res2mmio(res, 0, 0);
-	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+	printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
 
 	if (RCBA32(CIR31) & (1 << 31)) {
 		reg32 = pci_read_config32(dev, 0x120);