commit b499c1f01448a352a14a9cb10e82e7f6ca167bd9
author Felix Held <felix-coreboot@felixheld.de> Tue Dec 12 20:39:38 2023 +0100
committer Felix Held <felix-coreboot@felixheld.de> Fri Dec 15 09:30:20 2023 +0000
tree 21355f860dca071b89122b9cbb44a8c14e137097
parent 80434a6984db3ec3967c3cc574f1b2a956a053b1

soc/amd/genoa: Hook up IVRS generation

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I0a6eaf43ab6da4bb4a0cc0bbefb5b75c206348f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/soc/amd/genoa/Kconfig

diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig
index f780e06..28774cc 100644
--- a/src/soc/amd/genoa/Kconfig
+++ b/src/soc/amd/genoa/Kconfig
@@ -15,6 +15,7 @@
 	select SOC_AMD_COMMON_BLOCK_ACPI
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 	select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
+	select SOC_AMD_COMMON_BLOCK_ACPI_IVRS
 	select SOC_AMD_COMMON_BLOCK_AOAC
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
 	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H

src/soc/amd/genoa/acpi.c

diff --git a/src/soc/amd/genoa/acpi.c b/src/soc/amd/genoa/acpi.c
index 1f7b7bf..2f7af7a 100644
--- a/src/soc/amd/genoa/acpi.c
+++ b/src/soc/amd/genoa/acpi.c
@@ -9,6 +9,8 @@
 #include <amdblocks/data_fabric.h>
 #include <arch/ioapic.h>
 #include <console/console.h>
+#include <device/device.h>
+#include <soc/acpi.h>
 #include <vendorcode/amd/opensil/genoa_poc/opensil.h>
 
 /* TODO: this can go in a common place */
@@ -53,6 +55,20 @@
 	fadt->x_firmware_ctl_h = 0;
 }
 
+unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current,
+				    struct acpi_rsdp *rsdp)
+{
+	/* IVRS */
+	acpi_ivrs_t *ivrs;
+	current = acpi_align_current(current);
+	ivrs = (acpi_ivrs_t *)current;
+	acpi_create_ivrs(ivrs, acpi_fill_ivrs);
+	current += ivrs->header.length;
+	acpi_add_table(rsdp, ivrs);
+
+	return current;
+}
+
 /* There are only the following 2 C-states reported by the reference firmware */
 const acpi_cstate_t cstate_cfg_table[] = {
 	[0] = {

src/soc/amd/genoa/chip.c

diff --git a/src/soc/amd/genoa/chip.c b/src/soc/amd/genoa/chip.c
index 46f43d1..d32d3ae 100644
--- a/src/soc/amd/genoa/chip.c
+++ b/src/soc/amd/genoa/chip.c
@@ -1,9 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
+#include <soc/southbridge.h>
+#include <soc/acpi.h>
 
 static void soc_init(void *chip_info)
 {
+	default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
 }
 
 static void soc_final(void *chip_info)

src/soc/amd/genoa/include/soc/acpi.h

diff --git a/src/soc/amd/genoa/include/soc/acpi.h b/src/soc/amd/genoa/include/soc/acpi.h
index 51fa91e..5c0efa5 100644
--- a/src/soc/amd/genoa/include/soc/acpi.h
+++ b/src/soc/amd/genoa/include/soc/acpi.h
@@ -3,6 +3,12 @@
 #ifndef AMD_GENOA_ACPI_H
 #define AMD_GENOA_ACPI_H
 
+#include <acpi/acpi.h>
+#include <device/device.h>
+
 #define ACPI_SCI_IRQ 9
 
+unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current,
+				    struct acpi_rsdp *rsdp);
+
 #endif /* AMD_GENOA_ACPI_H */