soc/intel: generate SSDT instead of using GNVS for SGX
GNVS should not be used for values that are static at runtime. Thus,
use SSDT for the SGX fields.
Change-Id: Icf9f035e0c2b8617eef82fb043293bcb913e3012
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 4f5029e..0e60771 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -12,7 +12,6 @@
#include <gpio.h>
#include <intelblocks/acpi.h>
#include <intelblocks/pmclib.h>
-#include <intelblocks/sgx.h>
#include <intelblocks/p2sb.h>
#include <soc/iomap.h>
#include <soc/pm.h>
@@ -88,9 +87,6 @@
gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio);
}
- if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
- sgx_fill_gnvs(gnvs);
-
/* Fill in Above 4GB MMIO resource */
sa_fill_gnvs(gnvs);
}
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 225e9db..41f2409 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -23,9 +23,6 @@
SCDP, 8, // 0x29 - SD_CD GPIO portid
SCDO, 8, // 0x2A - GPIO pad offset relative to the community
UIOR, 8, // 0x2B - UART debug controller init on S3 resume
- EPCS, 8, // 0x2C - SGX Enabled status
- EMNA, 64, // 0x2D - 0x34 EPC base address
- ELNG, 64, // 0x35 - 0x3C EPC Length
- A4GB, 64, // 0x3D - 0x44 Base of above 4GB MMIO Resource
- A4GS, 64, // 0x45 - 0x4C Length of above 4GB MMIO Resource
+ A4GB, 64, // 0x2C - 0x33 Base of above 4GB MMIO Resource
+ A4GS, 64, // 0x34 - 0x3B Length of above 4GB MMIO Resource
}
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index b471748..a9e0230 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -28,11 +28,8 @@
uint8_t scdo; /* 0x2A - GPIO pad offset relative to the community */
uint8_t uior; /* 0x2B - UART debug controller init on S3
resume */
- uint8_t epcs; /* 0x2C - SGX Enabled status */
- uint64_t emna; /* 0x2D - 0x34 EPC base address */
- uint64_t elng; /* 0x35 - 0x3C EPC Length */
- uint64_t a4gb; /* 0x3D - 0x44 Base of above 4GB MMIO Resource */
- uint64_t a4gs; /* 0x45 - 0x4C Length of above 4GB MMIO Resource */
+ uint64_t a4gb; /* 0x2C - 0x33 Base of above 4GB MMIO Resource */
+ uint64_t a4gs; /* 0x34 - 0x3B Length of above 4GB MMIO Resource */
};
#endif /* _SOC_APOLLOLAKE_NVS_H_ */
diff --git a/src/soc/intel/common/acpi/sgx.asl b/src/soc/intel/common/acpi/sgx.asl
index 9aea7a8..cfd7f7e 100644
--- a/src/soc/intel/common/acpi/sgx.asl
+++ b/src/soc/intel/common/acpi/sgx.asl
@@ -6,6 +6,9 @@
// Secure Enclave memory
Device (EPC)
{
+ External (EPCS, IntObj)
+ External (EMNA, IntObj)
+ External (ELNG, IntObj)
Name (_HID, EISAID ("INT0E0C"))
Name (_STR, Unicode ("Enclave Page Cache 1.0"))
Name (_MLS, Package () {
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 1601777..b827c58 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -15,6 +15,7 @@
#include <intelblocks/acpi_wake_source.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pmclib.h>
+#include <intelblocks/sgx.h>
#include <intelblocks/uart.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
@@ -427,4 +428,7 @@
/* Add a method to notify processor nodes */
acpigen_write_processor_cnot(num_virt);
+
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
+ sgx_fill_ssdt();
}
diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index 003a5ce..ab63a5c 100644
--- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -25,7 +25,4 @@
A4GB, 64, // 0x30 - 0x37 Base of above 4GB MMIO Resource
A4GS, 64, // 0x38 - 0x3f Length of above 4GB MMIO Resource
, 64, // 0x40 - 0x47 Hest log buffer (used in SMM, not ASL code)
- EPCS, 8, // 0x48 - SGX enabled status
- EMNA, 64, // 0x49 - 0x50 EPC base address
- ELNG, 64, // 0x51 - 0x58 EPC length
}
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index 3ebb08b..5adbdb8 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -27,10 +27,6 @@
u64 a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */
u64 a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */
u64 hest_log_addr; /* 0x40 - 47 err log addr (used in SMM, not ASL code) */
- /* SGX */
- u8 epcs; /* 0x48 - SGX enabled status */
- u64 emna; /* 0x49 - 0x50 EPC base address */
- u64 elng; /* 0x51 - 0x58 EPC length */
};
#endif
diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h
index 56e4a16..fc7282f 100644
--- a/src/soc/intel/common/block/include/intelblocks/sgx.h
+++ b/src/soc/intel/common/block/include/intelblocks/sgx.h
@@ -17,7 +17,7 @@
*/
void sgx_configure(void *unused);
-/* Fill GNVS data with SGX status, EPC base and length */
-void sgx_fill_gnvs(struct global_nvs *gnvs);
+/* Fill SSDT for SGX status, EPC base and length */
+void sgx_fill_ssdt(void);
#endif /* SOC_INTEL_COMMON_BLOCK_SGX_H */
diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c
index e0dcd85..d15fc0f 100644
--- a/src/soc/intel/common/block/sgx/sgx.c
+++ b/src/soc/intel/common/block/sgx/sgx.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpigen.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
@@ -10,7 +11,6 @@
#include <intelblocks/sgx.h>
#include <intelblocks/systemagent.h>
#include <soc/cpu.h>
-#include <soc/nvs.h>
#include <soc/pci_devs.h>
static inline uint64_t sgx_resource(uint32_t low, uint32_t high)
@@ -235,31 +235,40 @@
activate_sgx();
}
-void sgx_fill_gnvs(struct global_nvs *gnvs)
+void sgx_fill_ssdt(void)
{
+ bool epcs = false;
struct cpuid_result cpuid_regs;
+ uint64_t emna = 0, elng = 0;
- if (!is_sgx_supported()) {
- printk(BIOS_DEBUG,
- "SGX: not supported. skip gnvs fill\n");
- return;
+ if (is_sgx_supported()) {
+ /*
+ * Get EPC base and size.
+ * Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 or
+ * Higher for enumeration of SGX Resources. Same Table mentions
+ * about return values of the CPUID
+ */
+ cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF,
+ SGX_RESOURCE_ENUM_CPUID_SUBLEAF);
+
+ if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) {
+ /* EPC section enumerated */
+ epcs = true;
+ emna = sgx_resource(cpuid_regs.eax, cpuid_regs.ebx);
+ elng = sgx_resource(cpuid_regs.ecx, cpuid_regs.edx);
+ }
+
+ printk(BIOS_DEBUG, "SGX: EPC status = %d base = 0x%llx len = 0x%llx\n",
+ epcs, emna, elng);
+ } else {
+ printk(BIOS_DEBUG, "SGX: not supported.\n");
}
- /* Get EPC base and size.
- * Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 or
- * Higher for enumeration of SGX Resources. Same Table mentions
- * about return values of the CPUID */
- cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF,
- SGX_RESOURCE_ENUM_CPUID_SUBLEAF);
-
- if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) {
- /* EPC section enumerated */
- gnvs->epcs = 1;
- gnvs->emna = sgx_resource(cpuid_regs.eax, cpuid_regs.ebx);
- gnvs->elng = sgx_resource(cpuid_regs.ecx, cpuid_regs.edx);
+ acpigen_write_scope("\\_SB.EPC");
+ {
+ acpigen_write_name_byte("EPCS", epcs);
+ acpigen_write_name_qword("EMNA", emna);
+ acpigen_write_name_qword("ELNG", elng);
}
-
- printk(BIOS_DEBUG,
- "SGX: gnvs EPC status = %d base = 0x%llx len = 0x%llx\n",
- gnvs->epcs, gnvs->emna, gnvs->elng);
+ acpigen_pop_len();
}
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 4794a99..fc2b65d 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -13,7 +13,6 @@
#include <intelblocks/acpi_wake_source.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
-#include <intelblocks/sgx.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pm.h>
@@ -179,9 +178,6 @@
gnvs->u2we = config->usb2_wake_enable_bitmap;
gnvs->u3we = config->usb3_wake_enable_bitmap;
- if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
- sgx_fill_gnvs(gnvs);
-
/* Fill in Above 4GB MMIO resource */
sa_fill_gnvs(gnvs);
}