mb/google/hatch: Add Kaisa variant
A verbatim copy of variants/puff
V.2: rebased on duffy.
BUG=b:152951180
BRANCH=none
TEST=none
Change-Id: I7ea28e96c8b6867e17097a8bfab848928195654d
Signed-off-by: Andrew McRae <amcrae@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 90c8e38..b284ffe 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -100,6 +100,7 @@
default "Helios" if BOARD_GOOGLE_HELIOS
default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP
default "Jinlon" if BOARD_GOOGLE_JINLON
+ default "Kaisa" if BOARD_GOOGLE_KAISA
default "Kindred" if BOARD_GOOGLE_KINDRED
default "Kohaku" if BOARD_GOOGLE_KOHAKU
default "Mushu" if BOARD_GOOGLE_MUSHU
@@ -127,6 +128,7 @@
default "helios" if BOARD_GOOGLE_HELIOS
default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP
default "jinlon" if BOARD_GOOGLE_JINLON
+ default "kaisa" if BOARD_GOOGLE_KAISA
default "kindred" if BOARD_GOOGLE_KINDRED
default "kohaku" if BOARD_GOOGLE_KOHAKU
default "mushu" if BOARD_GOOGLE_MUSHU
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name
index 7eebc2f..0713d13 100644
--- a/src/mainboard/google/hatch/Kconfig.name
+++ b/src/mainboard/google/hatch/Kconfig.name
@@ -33,6 +33,14 @@
select BOARD_ROMSIZE_KB_16384
select DRIVERS_GFX_GENERIC
+config BOARD_GOOGLE_KAISA
+ bool "-> Kaisa"
+ select BOARD_GOOGLE_BASEBOARD_HATCH
+ select BOARD_ROMSIZE_KB_32768
+ select ROMSTAGE_SPD_SMBUS
+ select SPD_READ_BY_WORD
+ select VBOOT_EC_EFS
+
config BOARD_GOOGLE_KOHAKU
bool "-> Kohaku"
select BOARD_GOOGLE_BASEBOARD_HATCH
diff --git a/src/mainboard/google/hatch/variants/kaisa/Makefile.inc b/src/mainboard/google/hatch/variants/kaisa/Makefile.inc
new file mode 100644
index 0000000..8cbad31
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/kaisa/Makefile.inc
@@ -0,0 +1,16 @@
+## This file is part of the coreboot project.
+##
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-y += gpio.c
+ramstage-y += mainboard.c
+bootblock-y += gpio.c
diff --git a/src/mainboard/google/hatch/variants/kaisa/gpio.c b/src/mainboard/google/hatch/variants/kaisa/gpio.c
new file mode 100644
index 0000000..60842a4
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/kaisa/gpio.c
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+static const struct pad_config gpio_table[] = {
+ /* A16 : SD_OC_ODL */
+ PAD_CFG_GPI(GPP_A16, NONE, DEEP),
+ /* A18 : LAN_PE_ISOLATE_ODL */
+ PAD_CFG_GPO(GPP_A18, 1, DEEP),
+ /* A23 : M2_WLAN_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
+
+ /* B5 : LAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+
+ /* C0 : SMBCLK */
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+ /* C1 : SMBDATA */
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+ /* C6: M2_WLAN_WAKE_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE),
+ /* C7 : LAN_WAKE_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE),
+ /* C10 : PCH_PCON_RST_ODL */
+ PAD_CFG_GPO(GPP_C10, 1, DEEP),
+ /* C11 : PCH_PCON_PDB_ODL */
+ PAD_CFG_GPO(GPP_C11, 1, DEEP),
+ /* C15 : WLAN_OFF_L */
+ PAD_CFG_GPO(GPP_C15, 1, DEEP),
+
+ /* E2 : EN_PP_MST_OD */
+ PAD_CFG_GPO(GPP_E2, 1, DEEP),
+ /* E9 : USB_A0_OC_ODL */
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+ /* E10 : USB_A1_OC_ODL */
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+
+ /* F11 : EMMC_CMD */
+ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
+ /* F12 : EMMC_DATA0 */
+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+ /* F13 : EMMC_DATA1 */
+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+ /* F14 : EMMC_DATA2 */
+ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+ /* F15 : EMMC_DATA3 */
+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+ /* F16 : EMMC_DATA4 */
+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+ /* F17 : EMMC_DATA5 */
+ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+ /* F18 : EMMC_DATA6 */
+ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+ /* F19 : EMMC_DATA7 */
+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+ /* F20 : EMMC_RCLK */
+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+ /* F21 : EMMC_CLK */
+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+ /* F22 : EMMC_RST_L */
+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+
+ /* H4: PCH_I2C_PCON_SDA */
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+ /* H5: PCH_I2C_PCON_SCL */
+ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+ /* H22 : PWM_PP3300_BIOZZER */
+ PAD_CFG_GPO(GPP_H22, 0, DEEP),
+};
+
+const struct pad_config *override_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+ /* B14 : GPP_B14_STRAP */
+ PAD_NC(GPP_B14, NONE),
+ /* B22 : GPP_B22_STRAP */
+ PAD_NC(GPP_B22, NONE),
+ /* E19 : GPP_E19_STRAP */
+ PAD_NC(GPP_E19, NONE),
+ /* E21 : GPP_E21_STRAP */
+ PAD_NC(GPP_E21, NONE),
+ /* B15 : H1_SLAVE_SPI_CS_L */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ /* B16 : H1_SLAVE_SPI_CLK */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ /* B17 : H1_SLAVE_SPI_MISO_R */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ /* B18 : H1_SLAVE_SPI_MOSI_R */
+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ /* C14 : BT_DISABLE_L */
+ PAD_CFG_GPO(GPP_C14, 0, DEEP),
+ /* PCH_WP_OD */
+ PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+ /* C21 : H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+ /* C23 : WLAN_PE_RST# */
+ PAD_CFG_GPO(GPP_C23, 1, DEEP),
+ /* E1 : M2_SSD_PEDET */
+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
+ /* E5 : SATA_DEVSLP1 */
+ PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..2c44a82
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl
@@ -0,0 +1 @@
+#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h b/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h
new file mode 100644
index 0000000..5e2043f
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+#include <variant/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
+
+#define MAINBOARD_EC_SMI_EVENTS 0
+
+/* EC can wake from S5 with power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with power button */
+#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS)
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
+ (MAINBOARD_EC_S3_WAKE_EVENTS | \
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable cros_ec_keyb device */
+#define EC_ENABLE_MKBP_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/*
+ * Defines EC wake pin route.
+ * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE#
+ * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic.
+ */
+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
+
+/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
+#define EC_ENABLE_SYNC_IRQ
+
+#endif /* VARIANT_EC_H */
diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kaisa/include/variant/gpio.h
new file mode 100644
index 0000000..6c95847
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/kaisa/include/variant/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/hatch/variants/kaisa/mainboard.c b/src/mainboard/google/hatch/variants/kaisa/mainboard.c
new file mode 100644
index 0000000..e8098b9
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/kaisa/mainboard.c
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <delay.h>
+#include <device/device.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
+#include <timer.h>
+
+#define GPIO_HDMI_HPD GPP_E13
+#define GPIO_DP_HPD GPP_E14
+
+/* TODO: This can be moved to common directory */
+static void wait_for_hpd(gpio_t gpio, long timeout)
+{
+ struct stopwatch sw;
+
+ printk(BIOS_INFO, "Waiting for HPD\n");
+ stopwatch_init_msecs_expire(&sw, timeout);
+ while (!gpio_get(gpio)) {
+ if (stopwatch_expired(&sw)) {
+ printk(BIOS_WARNING,
+ "HPD not ready after %ldms. Abort.\n", timeout);
+ return;
+ }
+ mdelay(200);
+ }
+ printk(BIOS_INFO, "HPD ready after %lu ms\n",
+ stopwatch_duration_msecs(&sw));
+}
+
+void variant_ramstage_init(void)
+{
+ static const long display_timeout_ms = 3000;
+
+ /* This is reconfigured back to whatever FSP-S expects by
+ gpio_configure_pads. */
+ gpio_input(GPIO_HDMI_HPD);
+ gpio_input(GPIO_DP_HPD);
+ if (display_init_required()
+ && !gpio_get(GPIO_HDMI_HPD)
+ && !gpio_get(GPIO_DP_HPD)) {
+ /* This has to be done before FSP-S runs. */
+ if (google_chromeec_wait_for_displayport(display_timeout_ms))
+ wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);
+ }
+}
+
+/*
+ * For type-C chargers, set PL2 to 90% of max power to account for
+ * cable loss and FET Rdson loss in the path from the source.
+ */
+#define SET_PSYSPL2(w) (9 * (w) / 10)
+
+#define PUFF_PL2 (35)
+
+#define PUFF_PSYSPL2 (58)
+
+#define PUFF_MAX_TIME_WINDOW 6
+#define PUFF_MIN_DUTYCYCLE 4
+
+/*
+ * mainboard_set_power_limits
+ *
+ * Set Pl2 and SysPl2 values based on detected charger.
+ * Values are defined below but we use U22 value for all SKUs for now.
+ * definitions:
+ * x = no value entered. Use default value in parenthesis.
+ * will set 0 to anything that shouldn't be set.
+ * n = max value of power adapter.
+ * +-------------+-----+---------+-----------+-------+
+ * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 |
+ * +-------------+-----+---------+-----------+-------+
+ * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) |
+ * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) |
+ * +-------------+-----+---------+-----------+-------+
+ * For USB C charger:
+ * +-------------+-----+---------+---------+-------+
+ * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 |
+ * +-------------+-----+---------+---------+-------+
+ * | 60 (U42) | 44 | 54 | 54 | 54 |
+ * | 60 (U22) | 29 | 54 | 54 | x(43) |
+ * | n (U42) | 44 | .9n | .9n | .9n |
+ * | n (U22) | 29 | .9n | .9n | x(43) |
+ * +-------------+-----+---------+---------+-------+
+ */
+static void mainboard_set_power_limits(config_t *conf)
+{
+ enum usb_chg_type type;
+ u32 watts;
+ u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22
+ int rv = google_chromeec_get_usb_pd_power_info(&type, &watts);
+
+ /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/
+ conf->tdp_psyspl3 = 0;
+ conf->tdp_pl4 = 0;
+
+ if (rv == 0 && type == USB_CHG_TYPE_PD) {
+ /* Detected USB-PD. Base on max value of adapter */
+ psyspl2 = watts;
+ conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2);
+ /* set max possible time window */
+ conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW;
+ /* set minimum duty cycle */
+ conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE;
+ conf->tdp_pl4 = SET_PSYSPL2(psyspl2);
+ }
+
+ conf->tdp_pl2_override = PUFF_PL2;
+ /* set psyspl2 to 90% of max adapter power */
+ conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2);
+}
+
+void variant_mainboard_enable(struct device *dev)
+{
+ config_t *conf = config_of_soc();
+ mainboard_set_power_limits(conf);
+}
diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
new file mode 100644
index 0000000..e09d0c4
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
@@ -0,0 +1,371 @@
+chip soc/intel/cannonlake
+ # Enable heci communication
+ register "HeciEnabled" = "1"
+
+ # Auto-switch between X4 NVMe and X2 NVMe.
+ register "TetonGlacierMode" = "1"
+
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ [PchSerialIoIndexSPI0] = PchSerialIoPci,
+ [PchSerialIoIndexSPI1] = PchSerialIoPci,
+ [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ # USB configuration
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
+ register "usb2_ports[2]" = "{
+ .enable = 1,
+ .ocpin = OC3,
+ .tx_bias = USB2_BIAS_0MV,
+ .tx_emp_enable = USB2_PRE_EMP_ON,
+ .pre_emp_bias = USB2_BIAS_28P15MV,
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+ }" # Type-A Port 3
+ register "usb2_ports[3]" = "{
+ .enable = 1,
+ .ocpin = OC1,
+ .tx_bias = USB2_BIAS_0MV,
+ .tx_emp_enable = USB2_PRE_EMP_ON,
+ .pre_emp_bias = USB2_BIAS_28P15MV,
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+ }" # Type-A Port 1
+ register "usb2_ports[4]" = "{
+ .enable = 1,
+ .ocpin = OC_SKIP,
+ .tx_bias = USB2_BIAS_0MV,
+ .tx_emp_enable = USB2_PRE_EMP_ON,
+ .pre_emp_bias = USB2_BIAS_28P15MV,
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+ }" # Type-A Port 4
+ register "usb2_ports[5]" = "{
+ .enable = 1,
+ .ocpin = OC0,
+ .tx_bias = USB2_BIAS_0MV,
+ .tx_emp_enable = USB2_PRE_EMP_ON,
+ .pre_emp_bias = USB2_BIAS_28P15MV,
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+ }" # Type-A port 0
+ register "usb2_ports[6]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[7]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[9]" = "{
+ .enable = 1,
+ .ocpin = OC_SKIP,
+ .tx_bias = USB2_BIAS_0MV,
+ .tx_emp_enable = USB2_PRE_EMP_ON,
+ .pre_emp_bias = USB2_BIAS_28P15MV,
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+ }" # BT
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
+
+ # Enable eMMC HS400
+ register "ScsEmmcHs400Enabled" = "1"
+
+ # EMMC Tx CMD Delay
+ # Refer to EDS-Vol2-14.3.7.
+ # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
+ # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
+ register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
+
+ # EMMC TX DATA Delay 1
+ # Refer to EDS-Vol2-14.3.8.
+ # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
+ # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
+ register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911"
+
+ # EMMC TX DATA Delay 2
+ # Refer to EDS-Vol2-14.3.9.
+ # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
+ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
+ # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
+ register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828"
+
+ # EMMC RX CMD/DATA Delay 1
+ # Refer to EDS-Vol2-14.3.10.
+ # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
+ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
+ # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
+ register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b"
+
+ # EMMC RX CMD/DATA Delay 2
+ # Refer to EDS-Vol2-14.3.12.
+ # [17:16] stands for Rx Clock before Output Buffer,
+ # 00: Rx clock after output buffer,
+ # 01: Rx clock before output buffer,
+ # 10: Automatic selection based on working mode.
+ # 11: Reserved
+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
+ # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
+ register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D"
+
+ # EMMC Rx Strobe Delay
+ # Refer to EDS-Vol2-14.3.11.
+ # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
+ # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
+ register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"
+
+ # Intel HDA - disable I2S Audio SSP1 and DMIC0 as kaisa variant does not have them.
+ register "PchHdaAudioLinkSsp1" = "0"
+ register "PchHdaAudioLinkDmic0" = "0"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| I2C0 | RFU |
+ #| I2C2 | PS175 |
+ #| I2C3 | MST |
+ #| I2C4 | Audio |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 0,
+ .fall_time_ns = 0,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 0,
+ .fall_time_ns = 0,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 0,
+ .fall_time_ns = 0,
+ },
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 60,
+ .fall_time_ns = 60,
+ },
+ }"
+
+ # PCIe port 7 for LAN
+ register "PcieRpEnable[6]" = "1"
+ register "PcieRpLtrEnable[6]" = "1"
+ # PCIe port 11 (x2) for NVMe hybrid storage devices
+ register "PcieRpEnable[10]" = "1"
+ register "PcieRpLtrEnable[10]" = "1"
+ # Uses CLK SRC 0
+ register "PcieClkSrcUsage[0]" = "6"
+ register "PcieClkSrcClkReq[0]" = "0"
+
+ # GPIO for SD card detect
+ register "sdcard_cd_gpio" = "vSD3_CD_B"
+
+ # SATA port 1 Gen3 Strength
+ # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB
+ register "sata_port[1].TxGen3DeEmphEnable" = "1"
+ register "sata_port[1].TxGen3DeEmph" = "0x20"
+
+ device domain 0 on
+ device pci 14.0 on
+ chip drivers/usb/acpi
+ device usb 0.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Front Left""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port Rear""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ device usb 2.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Front Right""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Rear Right""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Rear Middle""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Rear Left""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.5 on end
+ end
+ chip drivers/usb/acpi
+ device usb 2.6 off end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Front Left""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Front Right""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Rear Right""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Rear""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ device usb 3.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Rear Left""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Rear Middle""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.5 on end
+ end
+ end
+ end
+ end # USB xHCI
+ device pci 15.0 off
+ # RFU - Reserved for Future Use.
+ end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 on end # I2C #2, PCON PS175.
+ device pci 15.3 on end # I2C #3, Realtek RTD2142.
+ device pci 19.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5682""
+ register "name" = ""RT58""
+ register "desc" = ""Realtek RT5682""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
+ register "property_count" = "1"
+ # Set the jd_src to RT5668_JD1 for jack detection
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on end
+ end
+ end #I2C #4
+ device pci 1a.0 on end # eMMC
+ device pci 1c.0 on
+ chip drivers/net
+ register "customized_leds" = "0x05af"
+ register "wake" = "GPE0_DW1_07" # GPP_C7
+ register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)"
+ register "stop_delay_ms" = "12" # NIC needs time to quiesce
+ register "stop_off_delay_ms" = "1"
+ register "has_power_resource" = "1"
+ register "device_index" = "0"
+ device pci 00.0 on end
+ end
+ end # FSP requires func0 be enabled.
+ device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1).
+ device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+ device pci 1e.3 off end # GSPI #1
+ end
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-------+-------+-------+-------+
+ #| Domain/Setting | SA | IA | GTUS | GTS |
+ #+----------------+-------+-------+-------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 5A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
+ #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
+ #+----------------+-------+-------+-------+-------+
+ #Note: IccMax settings are moved to SoC code
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = 0,
+ .voltage_limit = 1520,
+ .ac_loadline = 1004,
+ .dc_loadline = 1004,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = 0,
+ .voltage_limit = 1520,
+ .ac_loadline = 181,
+ .dc_loadline = 181,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = 0,
+ .voltage_limit = 1520,
+ .ac_loadline = 319,
+ .dc_loadline = 319,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = 0,
+ .voltage_limit = 1520,
+ .ac_loadline = 319,
+ .dc_loadline = 319,
+ }"
+
+end