soc/cavium/cn81xx: Use write{32,64}p()
Change-Id: I9c94f45264f541ce0849a53245534a10aaa5d854
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
diff --git a/src/soc/cavium/cn81xx/cpu.c b/src/soc/cavium/cn81xx/cpu.c
index 14aff58..43b64d5 100644
--- a/src/soc/cavium/cn81xx/cpu.c
+++ b/src/soc/cavium/cn81xx/cpu.c
@@ -72,7 +72,7 @@
return 1;
/* Write the address of the main entry point */
- write64((void *)MIO_BOOT_AP_JUMP, (uintptr_t)secondary_init);
+ write64p(MIO_BOOT_AP_JUMP, (uintptr_t)secondary_init);
/* Get coremask of cores in reset */
const uint64_t reset = read64p(RST_PP_RESET);
@@ -86,7 +86,7 @@
printk(BIOS_DEBUG, "CPU: Taking core %zu out of reset.\n", cpu);
/* Release core from reset */
- write64((void *)RST_PP_RESET, reset & ~coremask);
+ write64p(RST_PP_RESET, reset & ~coremask);
/* Wait for cores to finish coming out of reset */
udelay(1);