cmos: Rename the CMOS related functions.
Most of the code related to the mc146818 is not related to the RTC and is
really for managing the CMOS storage. Since we intend to add a generic API
for RTC drivers it's inconvenient for those functions to have an rtc_ prefix.
This CL renames those functions so they start with cmos_ instead. There are
some places where rtc_init was called with a comment that says something about
starting the RTC. That wasn't correct before (the RTC is always running), but
it looks a little odd now that the function is called cmos_init.
This CL also opportunistically cleans up some style problems in this file.
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/197794
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 9a9ad24888b185fb58965457704e326bb508d788)
Removed the addition of stdint.h to mc146818rtc.h since
types.h is now included. Changed rtc_init to cmos_init for
fsp_bd82x6x, fsp_rangeley, fsp_baytrail, ibexpeak, vortex86ex.
Change-Id: Id4b9f6bea93e8bd5eaef2cb17f296adb9697114c
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index 20212ef..1f60bc4 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -70,14 +70,14 @@
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
}
static void hudson_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c
index 8cabcab..718b40b 100644
--- a/src/southbridge/amd/amd8111/lpc.c
+++ b/src/southbridge/amd/amd8111/lpc.c
@@ -77,7 +77,7 @@
}
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index 42330ca..20da0733 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -80,14 +80,14 @@
{
printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n");
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
setup_i8259(); /* Initialize i8259 pic */
setup_i8254(); /* Initialize i8254 timers */
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index b132bf1..7d6e221 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -132,14 +132,14 @@
{
printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n");
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
setup_i8259(); /* Initialize i8259 pic */
setup_i8254(); /* Initialize i8254 timers */
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 7303bdc..8d9b4868 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -102,14 +102,14 @@
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n");
/* SB Configure HPET base and enable bit */
//- hpetInit(sb_config, &(sb_config->BuildParameters));
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
setup_i8259(); /* Initialize i8259 pic */
setup_i8254(); /* Initialize i8254 timers */
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index e305594..1f7eab87 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -245,7 +245,7 @@
msr.lo = RTC_MONA;
wrmsr(MDD_RTC_MONA_IND, msr);
- rtc_init(0);
+ cmos_init(0);
isa_dma_init();
}
diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c
index 7f1ca25..d8e63b55 100644
--- a/src/southbridge/amd/sb600/lpc.c
+++ b/src/southbridge/amd/sb600/lpc.c
@@ -63,7 +63,7 @@
byte &= ~(1 << 1);
pci_write_config8(dev, 0x78, byte);
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
}
static void sb600_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c
index 8de39a6..a8e72c2 100644
--- a/src/southbridge/amd/sb600/sm.c
+++ b/src/southbridge/amd/sb600/sm.c
@@ -169,7 +169,7 @@
/* ab index */
pci_write_config32(dev, 0xF0, AB_INDX);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/*3.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
abcfg_reg(0x10060, 9 << 17, 9 << 17);
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 6995861..173de83 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -90,7 +90,7 @@
}
#endif
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
}
void backup_top_of_ram(uint64_t ramtop)
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 0fb6556..8bb5378 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -197,7 +197,7 @@
/* ab index */
pci_write_config32(dev, 0xF0, AB_INDX);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* 4.3 Enabling Upstream DMA Access */
axcfg_reg(0x04, 1 << 2, 1 << 2);
diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c
index 12fd96f..7a4dd83 100644
--- a/src/southbridge/amd/sb800/lpc.c
+++ b/src/southbridge/amd/sb800/lpc.c
@@ -67,7 +67,7 @@
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
}
static void sb800_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index 315bc20..acdfb09 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -111,7 +111,7 @@
pm_iowrite(0xE2, (AB_INDX >> 16) & 0xFF);
pm_iowrite(0xE3, (AB_INDX >> 24) & 0xFF);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
byte = pm_ioread(0x8);
byte |= 1 << 2 | 1 << 4;
diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c
index 834f0a1..af79892 100644
--- a/src/southbridge/broadcom/bcm5785/lpc.c
+++ b/src/southbridge/broadcom/bcm5785/lpc.c
@@ -33,7 +33,7 @@
static void lpc_init(device_t dev)
{
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c
index a2b1246..d4f263b 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.c
+++ b/src/southbridge/dmp/vortex86ex/southbridge.c
@@ -595,7 +595,7 @@
pci_routing_fixup(dev);
fix_cmos_rtc_time();
- rtc_init(0);
+ cmos_init(0);
/* Check keyboard controller ready. If timeout, reload firmware code
* and try again.
*/
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 75b8a6c..0e3a4f6 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -294,7 +294,7 @@
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* CougarPoint PCH Power Management init */
diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c
index 67bcadc..b5b77ef 100644
--- a/src/southbridge/intel/esb6300/lpc.c
+++ b/src/southbridge/intel/esb6300/lpc.c
@@ -297,7 +297,7 @@
esb6300_gpio_init(dev);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index 2fc3ea7..e5d63b6 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -305,7 +305,7 @@
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* CougarPoint PCH Power Management init */
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index 0697785..bd3d12c 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -69,7 +69,7 @@
write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
}
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
void rangeley_sb_early_initialization(void)
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c
index 7c79e58..ba74f30 100644
--- a/src/southbridge/intel/i3100/lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
@@ -375,7 +375,7 @@
i3100_gpio_init(dev);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index 5605106..5261fba 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -64,7 +64,7 @@
u32 reg32;
/* Initialize the real time clock (RTC). */
- rtc_init(0);
+ cmos_init(0);
/*
* Enable special cycles, needed for soft poweroff.
diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c
index 212c95f..11519c1 100644
--- a/src/southbridge/intel/i82801ax/lpc.c
+++ b/src/southbridge/intel/i82801ax/lpc.c
@@ -190,7 +190,7 @@
}
reg32 = pci_read_config32(dev, GEN_STA);
rtc_failed |= reg32 & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
/* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c
index 13b1599..278d65c 100644
--- a/src/southbridge/intel/i82801bx/lpc.c
+++ b/src/southbridge/intel/i82801bx/lpc.c
@@ -205,7 +205,7 @@
}
reg32 = pci_read_config32(dev, GEN_STS);
rtc_failed |= reg32 & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
/* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c
index f9c0ece..f6c33b7 100644
--- a/src/southbridge/intel/i82801cx/lpc.c
+++ b/src/southbridge/intel/i82801cx/lpc.c
@@ -108,7 +108,7 @@
dword = pci_read_config32(dev, GEN_STS);
rtc_failed |= dword & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index de09b16..1b23fad 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -200,7 +200,7 @@
}
reg32 = pci_read_config32(dev, GEN_STS);
rtc_failed |= reg32 & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
/* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index fb1586e..1823e65 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -308,7 +308,7 @@
i82801ex_gpio_init(dev);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 80abb78..10e40be 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -294,7 +294,7 @@
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
static void enable_hpet(void)
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 8105a4d..664088c 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -326,7 +326,7 @@
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
static void enable_hpet(void)
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 31bb4e7..a833a3d 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -294,7 +294,7 @@
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
static void mobile5_pm_init(struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 64b835f..a202424 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -301,7 +301,7 @@
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* LynxPoint PCH Power Management init */
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index b68785a..9b6049c 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -162,7 +162,7 @@
outb(byte, 0x70);
/* Initialize the real time clock (RTC). */
- rtc_init(0);
+ cmos_init(0);
/* Initialize ISA DMA. */
isa_dma_init();
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index ef3c6f6..11c2c4f 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -152,7 +152,7 @@
outb(byte, 0x70);
/* Initialize the real time clock. */
- rtc_init(0);
+ cmos_init(0);
/* Initialize ISA DMA. */
isa_dma_init();
diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c
index 824bb6a..0e11c6f 100644
--- a/src/southbridge/sis/sis966/lpc.c
+++ b/src/southbridge/sis/sis966/lpc.c
@@ -148,7 +148,7 @@
}
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/via/vt8231/lpc.c b/src/southbridge/via/vt8231/lpc.c
index 40854db..c6b74fd 100644
--- a/src/southbridge/via/vt8231/lpc.c
+++ b/src/southbridge/via/vt8231/lpc.c
@@ -121,7 +121,7 @@
//ethernet_fixup();
// Start the rtc
- rtc_init(0);
+ cmos_init(0);
}
static void vt8231_read_resources(device_t dev)
diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c
index b355ad0..2c78481 100644
--- a/src/southbridge/via/vt8235/lpc.c
+++ b/src/southbridge/via/vt8235/lpc.c
@@ -209,7 +209,7 @@
pci_write_config8(dev, 0x40, 0x54);
// Start the rtc
- rtc_init(0);
+ cmos_init(0);
}
/* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 5ddd816..9e8f6f6 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -565,7 +565,7 @@
setup_pm(dev);
/* Start the RTC. */
- rtc_init(0);
+ cmos_init(0);
}
static void vt8237r_read_resources(device_t dev)