soc/intel/skylake: Add config for mbx command for Intersil VR C-state issues
Config for activating VR mailbox command for Intersil VR C-state issues.
0 - no mailbox command sent.
1 - VR mailbox command sent for IA/GT rails only.
2 - VR mailbox command sent for IA/GT/SA rails.
BUG=b:65499724
BRANCH=none
TEST= build and boot soraka.
Change-Id: Ibcced31b7ba473ffa7368c90c945d07a81a368d4
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 0ade01c..022306c 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -518,6 +518,14 @@
/* coreboot handles locking */
CHIPSET_LOCKDOWN_COREBOOT,
} chipset_lockdown;
+
+ /*
+ * Activates VR mailbox command for Intersil VR C-state issues.
+ * 0 - no mailbox command sent.
+ * 1 - VR mailbox command sent for IA/GT rails only.
+ * 2 - VR mailbox command sent for IA/GT/SA rails.
+ */
+ u8 IslVrCmd;
};
typedef struct soc_intel_skylake_config config_t;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index b1697ae..ac60125 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -271,6 +271,14 @@
*/
params->SendVrMbxCmd1 = config->SendVrMbxCmd;
+ /*
+ * Activates VR mailbox command for Intersil VR C-state issues.
+ * 0 - no mailbox command sent.
+ * 1 - VR mailbox command sent for IA/GT rails only.
+ * 2 - VR mailbox command sent for IA/GT/SA rails.
+ */
+ params->IslVrCmd = config->IslVrCmd;
+
/* Acoustic Noise Mitigation */
params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
params->SlowSlewRateForIa = config->SlowSlewRateForIa;